Lines Matching refs:index
121 static inline void hisi_dma_chan_write(void __iomem *base, u32 reg, u32 index,
124 writel_relaxed(val, base + reg + index * HISI_DMA_OFFSET);
141 static void hisi_dma_pause_dma(struct hisi_dma_dev *hdma_dev, u32 index,
144 void __iomem *addr = hdma_dev->base + HISI_DMA_CTRL0 + index *
150 static void hisi_dma_enable_dma(struct hisi_dma_dev *hdma_dev, u32 index,
153 void __iomem *addr = hdma_dev->base + HISI_DMA_CTRL0 + index *
174 static void hisi_dma_do_reset(struct hisi_dma_dev *hdma_dev, u32 index)
176 void __iomem *addr = hdma_dev->base + HISI_DMA_CTRL1 + index *
182 static void hisi_dma_reset_qp_point(struct hisi_dma_dev *hdma_dev, u32 index)
184 hisi_dma_chan_write(hdma_dev->base, HISI_DMA_SQ_TAIL_PTR, index, 0);
185 hisi_dma_chan_write(hdma_dev->base, HISI_DMA_CQ_HEAD_PTR, index, 0);
192 u32 index = chan->qp_num, tmp;
195 hisi_dma_pause_dma(hdma_dev, index, true);
196 hisi_dma_enable_dma(hdma_dev, index, false);
197 hisi_dma_mask_irq(hdma_dev, index);
200 HISI_DMA_Q_FSM_STS + index * HISI_DMA_OFFSET, tmp,
207 hisi_dma_do_reset(hdma_dev, index);
208 hisi_dma_reset_qp_point(hdma_dev, index);
209 hisi_dma_pause_dma(hdma_dev, index, false);
212 hisi_dma_enable_dma(hdma_dev, index, true);
213 hisi_dma_unmask_irq(hdma_dev, index);
217 HISI_DMA_Q_FSM_STS + index * HISI_DMA_OFFSET, tmp,
371 static void hisi_dma_init_hw_qp(struct hisi_dma_dev *hdma_dev, u32 index)
373 struct hisi_dma_chan *chan = &hdma_dev->chan[index];
378 hisi_dma_chan_write(base, HISI_DMA_SQ_BASE_L, index,
380 hisi_dma_chan_write(base, HISI_DMA_SQ_BASE_H, index,
382 hisi_dma_chan_write(base, HISI_DMA_CQ_BASE_L, index,
384 hisi_dma_chan_write(base, HISI_DMA_CQ_BASE_H, index,
388 hisi_dma_chan_write(base, HISI_DMA_SQ_DEPTH, index, hw_depth);
389 hisi_dma_chan_write(base, HISI_DMA_CQ_DEPTH, index, hw_depth);
392 hisi_dma_chan_write(base, HISI_DMA_SQ_TAIL_PTR, index, 0);
393 hisi_dma_chan_write(base, HISI_DMA_CQ_HEAD_PTR, index, 0);