Lines Matching refs:hdma_dev
90 struct hisi_dma_dev *hdma_dev;
141 static void hisi_dma_pause_dma(struct hisi_dma_dev *hdma_dev, u32 index,
144 void __iomem *addr = hdma_dev->base + HISI_DMA_CTRL0 + index *
150 static void hisi_dma_enable_dma(struct hisi_dma_dev *hdma_dev, u32 index,
153 void __iomem *addr = hdma_dev->base + HISI_DMA_CTRL0 + index *
159 static void hisi_dma_mask_irq(struct hisi_dma_dev *hdma_dev, u32 qp_index)
161 hisi_dma_chan_write(hdma_dev->base, HISI_DMA_INT_MSK, qp_index,
165 static void hisi_dma_unmask_irq(struct hisi_dma_dev *hdma_dev, u32 qp_index)
167 void __iomem *base = hdma_dev->base;
174 static void hisi_dma_do_reset(struct hisi_dma_dev *hdma_dev, u32 index)
176 void __iomem *addr = hdma_dev->base + HISI_DMA_CTRL1 + index *
182 static void hisi_dma_reset_qp_point(struct hisi_dma_dev *hdma_dev, u32 index)
184 hisi_dma_chan_write(hdma_dev->base, HISI_DMA_SQ_TAIL_PTR, index, 0);
185 hisi_dma_chan_write(hdma_dev->base, HISI_DMA_CQ_HEAD_PTR, index, 0);
191 struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
195 hisi_dma_pause_dma(hdma_dev, index, true);
196 hisi_dma_enable_dma(hdma_dev, index, false);
197 hisi_dma_mask_irq(hdma_dev, index);
199 ret = readl_relaxed_poll_timeout(hdma_dev->base +
203 dev_err(&hdma_dev->pdev->dev, "disable channel timeout!\n");
207 hisi_dma_do_reset(hdma_dev, index);
208 hisi_dma_reset_qp_point(hdma_dev, index);
209 hisi_dma_pause_dma(hdma_dev, index, false);
212 hisi_dma_enable_dma(hdma_dev, index, true);
213 hisi_dma_unmask_irq(hdma_dev, index);
216 ret = readl_relaxed_poll_timeout(hdma_dev->base +
220 dev_err(&hdma_dev->pdev->dev, "reset channel timeout!\n");
228 struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
233 memset(chan->sq, 0, sizeof(struct hisi_dma_sqe) * hdma_dev->chan_depth);
234 memset(chan->cq, 0, sizeof(struct hisi_dma_cqe) * hdma_dev->chan_depth);
273 struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
296 chan->sq_tail = (chan->sq_tail + 1) % hdma_dev->chan_depth;
299 hisi_dma_chan_write(hdma_dev->base, HISI_DMA_SQ_TAIL_PTR, chan->qp_num,
324 hisi_dma_pause_dma(chan->hdma_dev, chan->qp_num, true);
335 hisi_dma_pause_dma(chan->hdma_dev, chan->qp_num, false);
347 static int hisi_dma_alloc_qps_mem(struct hisi_dma_dev *hdma_dev)
349 size_t sq_size = sizeof(struct hisi_dma_sqe) * hdma_dev->chan_depth;
350 size_t cq_size = sizeof(struct hisi_dma_cqe) * hdma_dev->chan_depth;
351 struct device *dev = &hdma_dev->pdev->dev;
355 for (i = 0; i < hdma_dev->chan_num; i++) {
356 chan = &hdma_dev->chan[i];
371 static void hisi_dma_init_hw_qp(struct hisi_dma_dev *hdma_dev, u32 index)
373 struct hisi_dma_chan *chan = &hdma_dev->chan[index];
374 u32 hw_depth = hdma_dev->chan_depth - 1;
375 void __iomem *base = hdma_dev->base;
396 static void hisi_dma_enable_qp(struct hisi_dma_dev *hdma_dev, u32 qp_index)
398 hisi_dma_init_hw_qp(hdma_dev, qp_index);
399 hisi_dma_unmask_irq(hdma_dev, qp_index);
400 hisi_dma_enable_dma(hdma_dev, qp_index, true);
403 static void hisi_dma_disable_qp(struct hisi_dma_dev *hdma_dev, u32 qp_index)
405 hisi_dma_reset_or_disable_hw_chan(&hdma_dev->chan[qp_index], true);
408 static void hisi_dma_enable_qps(struct hisi_dma_dev *hdma_dev)
412 for (i = 0; i < hdma_dev->chan_num; i++) {
413 hdma_dev->chan[i].qp_num = i;
414 hdma_dev->chan[i].hdma_dev = hdma_dev;
415 hdma_dev->chan[i].vc.desc_free = hisi_dma_desc_free;
416 vchan_init(&hdma_dev->chan[i].vc, &hdma_dev->dma_dev);
417 hisi_dma_enable_qp(hdma_dev, i);
421 static void hisi_dma_disable_qps(struct hisi_dma_dev *hdma_dev)
425 for (i = 0; i < hdma_dev->chan_num; i++) {
426 hisi_dma_disable_qp(hdma_dev, i);
427 tasklet_kill(&hdma_dev->chan[i].vc.task);
434 struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
444 chan->cq_head = (chan->cq_head + 1) % hdma_dev->chan_depth;
445 hisi_dma_chan_write(hdma_dev->base, HISI_DMA_CQ_HEAD_PTR,
451 dev_err(&hdma_dev->pdev->dev, "task error!\n");
460 static int hisi_dma_request_qps_irq(struct hisi_dma_dev *hdma_dev)
462 struct pci_dev *pdev = hdma_dev->pdev;
465 for (i = 0; i < hdma_dev->chan_num; i++) {
468 &hdma_dev->chan[i]);
477 static int hisi_dma_enable_hw_channels(struct hisi_dma_dev *hdma_dev)
481 ret = hisi_dma_alloc_qps_mem(hdma_dev);
483 dev_err(&hdma_dev->pdev->dev, "fail to allocate qp memory!\n");
487 ret = hisi_dma_request_qps_irq(hdma_dev);
489 dev_err(&hdma_dev->pdev->dev, "fail to request qp irq!\n");
493 hisi_dma_enable_qps(hdma_dev);
503 static void hisi_dma_set_mode(struct hisi_dma_dev *hdma_dev,
506 writel_relaxed(mode == RC ? 1 : 0, hdma_dev->base + HISI_DMA_MODE);
512 struct hisi_dma_dev *hdma_dev;
536 hdma_dev = devm_kzalloc(dev, struct_size(hdma_dev, chan, HISI_DMA_CHAN_NUM), GFP_KERNEL);
537 if (!hdma_dev)
540 hdma_dev->base = pcim_iomap_table(pdev)[PCI_BAR_2];
541 hdma_dev->pdev = pdev;
542 hdma_dev->chan_num = HISI_DMA_CHAN_NUM;
543 hdma_dev->chan_depth = HISI_DMA_Q_DEPTH_VAL;
545 pci_set_drvdata(pdev, hdma_dev);
559 dma_dev = &hdma_dev->dma_dev;
571 hisi_dma_set_mode(hdma_dev, RC);
573 ret = hisi_dma_enable_hw_channels(hdma_dev);
580 hdma_dev);