Lines Matching refs:chan
108 struct hisi_dma_chan chan[];
113 return container_of(c, struct hisi_dma_chan, vc.chan);
188 static void hisi_dma_reset_or_disable_hw_chan(struct hisi_dma_chan *chan,
191 struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
192 u32 index = chan->qp_num, tmp;
227 struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
228 struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
230 hisi_dma_reset_or_disable_hw_chan(chan, false);
231 vchan_free_chan_resources(&chan->vc);
233 memset(chan->sq, 0, sizeof(struct hisi_dma_sqe) * hdma_dev->chan_depth);
234 memset(chan->cq, 0, sizeof(struct hisi_dma_cqe) * hdma_dev->chan_depth);
235 chan->sq_tail = 0;
236 chan->cq_head = 0;
237 chan->status = DISABLE;
249 struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
260 return vchan_tx_prep(&chan->vc, &desc->vd, flags);
270 static void hisi_dma_start_transfer(struct hisi_dma_chan *chan)
272 struct hisi_dma_sqe *sqe = chan->sq + chan->sq_tail;
273 struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
277 vd = vchan_next_desc(&chan->vc);
279 chan->desc = NULL;
284 chan->desc = desc;
296 chan->sq_tail = (chan->sq_tail + 1) % hdma_dev->chan_depth;
299 hisi_dma_chan_write(hdma_dev->base, HISI_DMA_SQ_TAIL_PTR, chan->qp_num,
300 chan->sq_tail);
305 struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
308 spin_lock_irqsave(&chan->vc.lock, flags);
310 if (vchan_issue_pending(&chan->vc) && !chan->desc)
311 hisi_dma_start_transfer(chan);
313 spin_unlock_irqrestore(&chan->vc.lock, flags);
318 struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
322 spin_lock_irqsave(&chan->vc.lock, flags);
324 hisi_dma_pause_dma(chan->hdma_dev, chan->qp_num, true);
325 if (chan->desc) {
326 vchan_terminate_vdesc(&chan->desc->vd);
327 chan->desc = NULL;
330 vchan_get_all_descriptors(&chan->vc, &head);
332 spin_unlock_irqrestore(&chan->vc.lock, flags);
334 vchan_dma_desc_free_list(&chan->vc, &head);
335 hisi_dma_pause_dma(chan->hdma_dev, chan->qp_num, false);
342 struct hisi_dma_chan *chan = to_hisi_dma_chan(c);
344 vchan_synchronize(&chan->vc);
352 struct hisi_dma_chan *chan;
356 chan = &hdma_dev->chan[i];
357 chan->sq = dmam_alloc_coherent(dev, sq_size, &chan->sq_dma,
359 if (!chan->sq)
362 chan->cq = dmam_alloc_coherent(dev, cq_size, &chan->cq_dma,
364 if (!chan->cq)
373 struct hisi_dma_chan *chan = &hdma_dev->chan[index];
379 lower_32_bits(chan->sq_dma));
381 upper_32_bits(chan->sq_dma));
383 lower_32_bits(chan->cq_dma));
385 upper_32_bits(chan->cq_dma));
405 hisi_dma_reset_or_disable_hw_chan(&hdma_dev->chan[qp_index], true);
413 hdma_dev->chan[i].qp_num = i;
414 hdma_dev->chan[i].hdma_dev = hdma_dev;
415 hdma_dev->chan[i].vc.desc_free = hisi_dma_desc_free;
416 vchan_init(&hdma_dev->chan[i].vc, &hdma_dev->dma_dev);
427 tasklet_kill(&hdma_dev->chan[i].vc.task);
433 struct hisi_dma_chan *chan = data;
434 struct hisi_dma_dev *hdma_dev = chan->hdma_dev;
439 spin_lock_irqsave(&chan->vc.lock, flags);
441 desc = chan->desc;
442 cqe = chan->cq + chan->cq_head;
444 chan->cq_head = (chan->cq_head + 1) % hdma_dev->chan_depth;
446 chan->qp_num, chan->cq_head);
449 hisi_dma_start_transfer(chan);
455 spin_unlock_irqrestore(&chan->vc.lock, flags);
468 &hdma_dev->chan[i]);
536 hdma_dev = devm_kzalloc(dev, struct_size(hdma_dev, chan, HISI_DMA_CHAN_NUM), GFP_KERNEL);