Lines Matching refs:chan
38 #define chan_dbg(chan, fmt, arg...) \
39 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
40 #define chan_err(chan, fmt, arg...) \
41 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
49 static void set_sr(struct fsldma_chan *chan, u32 val)
51 FSL_DMA_OUT(chan, &chan->regs->sr, val, 32);
54 static u32 get_sr(struct fsldma_chan *chan)
56 return FSL_DMA_IN(chan, &chan->regs->sr, 32);
59 static void set_mr(struct fsldma_chan *chan, u32 val)
61 FSL_DMA_OUT(chan, &chan->regs->mr, val, 32);
64 static u32 get_mr(struct fsldma_chan *chan)
66 return FSL_DMA_IN(chan, &chan->regs->mr, 32);
69 static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
71 FSL_DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
74 static dma_addr_t get_cdar(struct fsldma_chan *chan)
76 return FSL_DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
79 static void set_bcr(struct fsldma_chan *chan, u32 val)
81 FSL_DMA_OUT(chan, &chan->regs->bcr, val, 32);
84 static u32 get_bcr(struct fsldma_chan *chan)
86 return FSL_DMA_IN(chan, &chan->regs->bcr, 32);
93 static void set_desc_cnt(struct fsldma_chan *chan,
96 hw->count = CPU_TO_DMA(chan, count, 32);
99 static void set_desc_src(struct fsldma_chan *chan,
104 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
106 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
109 static void set_desc_dst(struct fsldma_chan *chan,
114 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
116 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
119 static void set_desc_next(struct fsldma_chan *chan,
124 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
126 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
129 static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
133 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
136 desc->hw.next_ln_addr = CPU_TO_DMA(chan,
137 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
145 static void dma_init(struct fsldma_chan *chan)
148 set_mr(chan, 0);
150 switch (chan->feature & FSL_DMA_IP_MASK) {
157 set_mr(chan, FSL_DMA_MR_BWC | FSL_DMA_MR_EIE
165 set_mr(chan, FSL_DMA_MR_EOTIE | FSL_DMA_MR_PRC_RM);
170 static int dma_is_idle(struct fsldma_chan *chan)
172 u32 sr = get_sr(chan);
183 static void dma_start(struct fsldma_chan *chan)
187 mode = get_mr(chan);
189 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
190 set_bcr(chan, 0);
196 if (chan->feature & FSL_DMA_CHAN_START_EXT) {
203 set_mr(chan, mode);
206 static void dma_halt(struct fsldma_chan *chan)
212 mode = get_mr(chan);
219 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
221 set_mr(chan, mode);
228 set_mr(chan, mode);
232 if (dma_is_idle(chan))
238 if (!dma_is_idle(chan))
239 chan_err(chan, "DMA halt timeout!\n");
244 * @chan : Freescale DMA channel
253 static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
257 mode = get_mr(chan);
272 set_mr(chan, mode);
277 * @chan : Freescale DMA channel
286 static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
290 mode = get_mr(chan);
305 set_mr(chan, mode);
310 * @chan : Freescale DMA channel
320 static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
326 mode = get_mr(chan);
330 set_mr(chan, mode);
335 * @chan : Freescale DMA channel
342 static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
345 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
347 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
352 * @chan : Freescale DMA channel
360 static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
363 chan->feature |= FSL_DMA_CHAN_START_EXT;
365 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
370 struct fsldma_chan *chan;
375 chan = to_fsl_chan(dchan);
377 fsl_chan_toggle_ext_start(chan, enable);
382 static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
384 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
386 if (list_empty(&chan->ld_pending))
396 set_desc_next(chan, &tail->hw, desc->async_tx.phys);
403 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
408 struct fsldma_chan *chan = to_fsl_chan(tx->chan);
413 spin_lock_bh(&chan->desc_lock);
416 if (unlikely(chan->pm_state != RUNNING)) {
417 chan_dbg(chan, "cannot submit due to suspend\n");
418 spin_unlock_bh(&chan->desc_lock);
432 append_ld_queue(chan, desc);
434 spin_unlock_bh(&chan->desc_lock);
441 * @chan : Freescale DMA channel
444 static void fsl_dma_free_descriptor(struct fsldma_chan *chan,
448 chan_dbg(chan, "LD %p free\n", desc);
449 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
454 * @chan : Freescale DMA channel
458 static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
463 desc = dma_pool_zalloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
465 chan_dbg(chan, "out of memory for link descriptor\n");
470 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
474 chan_dbg(chan, "LD %p allocated\n", desc);
482 * @chan: Freescale DMA channel
487 static void fsldma_clean_completed_descriptor(struct fsldma_chan *chan)
492 list_for_each_entry_safe(desc, _desc, &chan->ld_completed, node)
494 fsl_dma_free_descriptor(chan, desc);
499 * @chan: Freescale DMA channel
506 static dma_cookie_t fsldma_run_tx_complete_actions(struct fsldma_chan *chan,
531 * @chan: Freescale DMA channel
537 static void fsldma_clean_running_descriptor(struct fsldma_chan *chan,
552 list_add_tail(&desc->node, &chan->ld_completed);
556 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
561 * @chan : Freescale DMA channel
564 * LOCKING: must hold chan->desc_lock
566 static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
574 if (list_empty(&chan->ld_pending)) {
575 chan_dbg(chan, "no pending LDs\n");
584 if (!chan->idle) {
585 chan_dbg(chan, "DMA controller still busy\n");
598 chan_dbg(chan, "idle, starting controller\n");
599 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
600 list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
607 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
610 mode = get_mr(chan);
612 set_mr(chan, mode);
619 set_cdar(chan, desc->async_tx.phys);
620 get_cdar(chan);
622 dma_start(chan);
623 chan->idle = false;
629 * @chan: Freescale DMA channel
635 static void fsldma_cleanup_descriptors(struct fsldma_chan *chan)
639 dma_addr_t curr_phys = get_cdar(chan);
642 fsldma_clean_completed_descriptor(chan);
645 list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
660 if (!dma_is_idle(chan))
664 cookie = fsldma_run_tx_complete_actions(chan, desc, cookie);
666 fsldma_clean_running_descriptor(chan, desc);
675 fsl_chan_xfer_ld_queue(chan);
678 chan->common.completed_cookie = cookie;
683 * @chan : Freescale DMA channel
691 struct fsldma_chan *chan = to_fsl_chan(dchan);
694 if (chan->desc_pool)
701 chan->desc_pool = dma_pool_create(chan->name, chan->dev,
704 if (!chan->desc_pool) {
705 chan_err(chan, "unable to allocate descriptor pool\n");
715 * @chan: Freescae DMA channel
718 * LOCKING: must hold chan->desc_lock
720 static void fsldma_free_desc_list(struct fsldma_chan *chan,
726 fsl_dma_free_descriptor(chan, desc);
729 static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
735 fsl_dma_free_descriptor(chan, desc);
740 * @chan : Freescale DMA channel
744 struct fsldma_chan *chan = to_fsl_chan(dchan);
746 chan_dbg(chan, "free all channel resources\n");
747 spin_lock_bh(&chan->desc_lock);
748 fsldma_cleanup_descriptors(chan);
749 fsldma_free_desc_list(chan, &chan->ld_pending);
750 fsldma_free_desc_list(chan, &chan->ld_running);
751 fsldma_free_desc_list(chan, &chan->ld_completed);
752 spin_unlock_bh(&chan->desc_lock);
754 dma_pool_destroy(chan->desc_pool);
755 chan->desc_pool = NULL;
763 struct fsldma_chan *chan;
773 chan = to_fsl_chan(dchan);
778 new = fsl_dma_alloc_descriptor(chan);
780 chan_err(chan, "%s\n", msg_ld_oom);
786 set_desc_cnt(chan, &new->hw, copy);
787 set_desc_src(chan, &new->hw, dma_src);
788 set_desc_dst(chan, &new->hw, dma_dst);
793 set_desc_next(chan, &prev->hw, new->async_tx.phys);
811 set_ld_eol(chan, new);
819 fsldma_free_desc_list_reverse(chan, &first->tx_list);
825 struct fsldma_chan *chan;
830 chan = to_fsl_chan(dchan);
832 spin_lock_bh(&chan->desc_lock);
835 dma_halt(chan);
838 fsldma_free_desc_list(chan, &chan->ld_pending);
839 fsldma_free_desc_list(chan, &chan->ld_running);
840 fsldma_free_desc_list(chan, &chan->ld_completed);
841 chan->idle = true;
843 spin_unlock_bh(&chan->desc_lock);
850 struct fsldma_chan *chan;
856 chan = to_fsl_chan(dchan);
859 if (!chan->set_request_count)
868 chan->set_request_count(chan, size);
875 * @chan : Freescale DMA channel
879 struct fsldma_chan *chan = to_fsl_chan(dchan);
881 spin_lock_bh(&chan->desc_lock);
882 fsl_chan_xfer_ld_queue(chan);
883 spin_unlock_bh(&chan->desc_lock);
888 * @chan : Freescale DMA channel
894 struct fsldma_chan *chan = to_fsl_chan(dchan);
901 spin_lock_bh(&chan->desc_lock);
902 fsldma_cleanup_descriptors(chan);
903 spin_unlock_bh(&chan->desc_lock);
914 struct fsldma_chan *chan = data;
918 stat = get_sr(chan);
919 set_sr(chan, stat);
920 chan_dbg(chan, "irq: stat = 0x%x\n", stat);
928 chan_err(chan, "Transfer Error!\n");
936 chan_dbg(chan, "irq: Programming Error INT\n");
938 if (get_bcr(chan) != 0)
939 chan_err(chan, "Programming Error!\n");
947 chan_dbg(chan, "irq: End-of-Chain link INT\n");
957 chan_dbg(chan, "irq: End-of-link INT\n");
962 if (!dma_is_idle(chan))
963 chan_err(chan, "irq: controller not idle!\n");
967 chan_err(chan, "irq: unhandled sr 0x%08x\n", stat);
974 tasklet_schedule(&chan->tasklet);
975 chan_dbg(chan, "irq: Exit\n");
981 struct fsldma_chan *chan = from_tasklet(chan, t, tasklet);
983 chan_dbg(chan, "tasklet entry\n");
985 spin_lock(&chan->desc_lock);
988 chan->idle = true;
991 fsldma_cleanup_descriptors(chan);
993 spin_unlock(&chan->desc_lock);
995 chan_dbg(chan, "tasklet exit\n");
1001 struct fsldma_chan *chan;
1012 chan = fdev->chan[i];
1013 if (!chan)
1017 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1018 fsldma_chan_irq(irq, chan);
1031 struct fsldma_chan *chan;
1041 chan = fdev->chan[i];
1042 if (chan && chan->irq) {
1043 chan_dbg(chan, "free per-channel IRQ\n");
1044 free_irq(chan->irq, chan);
1051 struct fsldma_chan *chan;
1065 chan = fdev->chan[i];
1066 if (!chan)
1069 if (!chan->irq) {
1070 chan_err(chan, "interrupts property missing in device tree\n");
1075 chan_dbg(chan, "request per-channel IRQ\n");
1076 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1077 "fsldma-chan", chan);
1079 chan_err(chan, "unable to request per-channel IRQ\n");
1088 chan = fdev->chan[i];
1089 if (!chan)
1092 if (!chan->irq)
1095 free_irq(chan->irq, chan);
1108 struct fsldma_chan *chan;
1113 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1114 if (!chan) {
1120 chan->regs = of_iomap(node, 0);
1121 if (!chan->regs) {
1133 chan->feature = feature;
1135 fdev->feature = chan->feature;
1141 WARN_ON(fdev->feature != chan->feature);
1143 chan->dev = fdev->dev;
1144 chan->id = (res.start & 0xfff) < 0x300 ?
1147 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
1153 fdev->chan[chan->id] = chan;
1154 tasklet_setup(&chan->tasklet, dma_do_tasklet);
1155 snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id);
1158 dma_init(chan);
1161 set_cdar(chan, 0);
1163 switch (chan->feature & FSL_DMA_IP_MASK) {
1165 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
1168 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1169 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1170 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1171 chan->set_request_count = fsl_chan_set_request_count;
1174 spin_lock_init(&chan->desc_lock);
1175 INIT_LIST_HEAD(&chan->ld_pending);
1176 INIT_LIST_HEAD(&chan->ld_running);
1177 INIT_LIST_HEAD(&chan->ld_completed);
1178 chan->idle = true;
1180 chan->pm_state = RUNNING;
1183 chan->common.device = &fdev->common;
1184 dma_cookie_init(&chan->common);
1187 chan->irq = irq_of_parse_and_map(node, 0);
1190 list_add_tail(&chan->common.device_node, &fdev->common.channels);
1192 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
1193 chan->irq ? chan->irq : fdev->irq);
1198 iounmap(chan->regs);
1200 kfree(chan);
1205 static void fsl_dma_chan_remove(struct fsldma_chan *chan)
1207 irq_dispose_mapping(chan->irq);
1208 list_del(&chan->common.device_node);
1209 iounmap(chan->regs);
1210 kfree(chan);
1297 if (fdev->chan[i])
1298 fsl_dma_chan_remove(fdev->chan[i]);
1319 if (fdev->chan[i])
1320 fsl_dma_chan_remove(fdev->chan[i]);
1334 struct fsldma_chan *chan;
1338 chan = fdev->chan[i];
1339 if (!chan)
1342 spin_lock_bh(&chan->desc_lock);
1343 if (unlikely(!chan->idle))
1345 chan->regs_save.mr = get_mr(chan);
1346 chan->pm_state = SUSPENDED;
1347 spin_unlock_bh(&chan->desc_lock);
1353 chan = fdev->chan[i];
1354 if (!chan)
1356 chan->pm_state = RUNNING;
1357 spin_unlock_bh(&chan->desc_lock);
1365 struct fsldma_chan *chan;
1370 chan = fdev->chan[i];
1371 if (!chan)
1374 spin_lock_bh(&chan->desc_lock);
1375 mode = chan->regs_save.mr
1377 set_mr(chan, mode);
1378 chan->pm_state = RUNNING;
1379 spin_unlock_bh(&chan->desc_lock);