Lines Matching refs:fsl_edma
32 struct fsl_edma_engine *fsl_edma = dev_id;
34 struct edma_regs *regs = &fsl_edma->regs;
37 intr = edma_readl(fsl_edma, regs->intl);
41 for (ch = 0; ch < fsl_edma->n_chans; ch++) {
43 edma_writeb(fsl_edma, EDMA_CINT_CINT(ch), regs->cint);
45 fsl_chan = &fsl_edma->chans[ch];
76 struct fsl_edma_engine *fsl_edma = dev_id;
78 struct edma_regs *regs = &fsl_edma->regs;
80 err = edma_readl(fsl_edma, regs->errl);
84 for (ch = 0; ch < fsl_edma->n_chans; ch++) {
86 fsl_edma_disable_request(&fsl_edma->chans[ch]);
87 edma_writeb(fsl_edma, EDMA_CERR_CERR(ch), regs->cerr);
88 fsl_edma->chans[ch].status = DMA_ERROR;
89 fsl_edma->chans[ch].idle = true;
106 struct fsl_edma_engine *fsl_edma = ofdma->of_dma_data;
109 u32 dmamux_nr = fsl_edma->drvdata->dmamuxs;
110 unsigned long chans_per_mux = fsl_edma->n_chans / dmamux_nr;
115 mutex_lock(&fsl_edma->fsl_edma_mutex);
116 list_for_each_entry_safe(chan, _chan, &fsl_edma->dma_dev.channels, device_node) {
127 mutex_unlock(&fsl_edma->fsl_edma_mutex);
132 mutex_unlock(&fsl_edma->fsl_edma_mutex);
137 fsl_edma_irq_init(struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
141 fsl_edma->txirq = platform_get_irq_byname(pdev, "edma-tx");
142 if (fsl_edma->txirq < 0)
143 return fsl_edma->txirq;
145 fsl_edma->errirq = platform_get_irq_byname(pdev, "edma-err");
146 if (fsl_edma->errirq < 0)
147 return fsl_edma->errirq;
149 if (fsl_edma->txirq == fsl_edma->errirq) {
150 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
151 fsl_edma_irq_handler, 0, "eDMA", fsl_edma);
157 ret = devm_request_irq(&pdev->dev, fsl_edma->txirq,
158 fsl_edma_tx_handler, 0, "eDMA tx", fsl_edma);
164 ret = devm_request_irq(&pdev->dev, fsl_edma->errirq,
165 fsl_edma_err_handler, 0, "eDMA err", fsl_edma);
177 struct fsl_edma_engine *fsl_edma)
199 sprintf(fsl_edma->chans[i].chan_name, "eDMA2-CH%02d", i);
205 0, "eDMA2-ERR", fsl_edma);
209 fsl_edma->chans[i].chan_name,
210 fsl_edma);
219 struct platform_device *pdev, struct fsl_edma_engine *fsl_edma)
221 if (fsl_edma->txirq == fsl_edma->errirq) {
222 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
224 devm_free_irq(&pdev->dev, fsl_edma->txirq, fsl_edma);
225 devm_free_irq(&pdev->dev, fsl_edma->errirq, fsl_edma);
229 static void fsl_disable_clocks(struct fsl_edma_engine *fsl_edma, int nr_clocks)
234 clk_disable_unprepare(fsl_edma->muxclk[i]);
270 struct fsl_edma_engine *fsl_edma;
291 len = sizeof(*fsl_edma) + sizeof(*fsl_chan) * chans;
292 fsl_edma = devm_kzalloc(&pdev->dev, len, GFP_KERNEL);
293 if (!fsl_edma)
296 fsl_edma->drvdata = drvdata;
297 fsl_edma->n_chans = chans;
298 mutex_init(&fsl_edma->fsl_edma_mutex);
301 fsl_edma->membase = devm_ioremap_resource(&pdev->dev, res);
302 if (IS_ERR(fsl_edma->membase))
303 return PTR_ERR(fsl_edma->membase);
305 fsl_edma_setup_regs(fsl_edma);
306 regs = &fsl_edma->regs;
309 fsl_edma->dmaclk = devm_clk_get(&pdev->dev, "dma");
310 if (IS_ERR(fsl_edma->dmaclk)) {
312 return PTR_ERR(fsl_edma->dmaclk);
315 ret = clk_prepare_enable(fsl_edma->dmaclk);
322 for (i = 0; i < fsl_edma->drvdata->dmamuxs; i++) {
326 fsl_edma->muxbase[i] = devm_ioremap_resource(&pdev->dev, res);
327 if (IS_ERR(fsl_edma->muxbase[i])) {
329 fsl_disable_clocks(fsl_edma, i);
330 return PTR_ERR(fsl_edma->muxbase[i]);
334 fsl_edma->muxclk[i] = devm_clk_get(&pdev->dev, clkname);
335 if (IS_ERR(fsl_edma->muxclk[i])) {
338 fsl_disable_clocks(fsl_edma, i);
339 return PTR_ERR(fsl_edma->muxclk[i]);
342 ret = clk_prepare_enable(fsl_edma->muxclk[i]);
345 fsl_disable_clocks(fsl_edma, i);
349 fsl_edma->big_endian = of_property_read_bool(np, "big-endian");
351 INIT_LIST_HEAD(&fsl_edma->dma_dev.channels);
352 for (i = 0; i < fsl_edma->n_chans; i++) {
353 struct fsl_edma_chan *fsl_chan = &fsl_edma->chans[i];
355 fsl_chan->edma = fsl_edma;
361 vchan_init(&fsl_chan->vchan, &fsl_edma->dma_dev);
363 edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr);
367 edma_writel(fsl_edma, ~0, regs->intl);
368 ret = fsl_edma->drvdata->setup_irq(pdev, fsl_edma);
372 dma_cap_set(DMA_PRIVATE, fsl_edma->dma_dev.cap_mask);
373 dma_cap_set(DMA_SLAVE, fsl_edma->dma_dev.cap_mask);
374 dma_cap_set(DMA_CYCLIC, fsl_edma->dma_dev.cap_mask);
376 fsl_edma->dma_dev.dev = &pdev->dev;
377 fsl_edma->dma_dev.device_alloc_chan_resources
379 fsl_edma->dma_dev.device_free_chan_resources
381 fsl_edma->dma_dev.device_tx_status = fsl_edma_tx_status;
382 fsl_edma->dma_dev.device_prep_slave_sg = fsl_edma_prep_slave_sg;
383 fsl_edma->dma_dev.device_prep_dma_cyclic = fsl_edma_prep_dma_cyclic;
384 fsl_edma->dma_dev.device_config = fsl_edma_slave_config;
385 fsl_edma->dma_dev.device_pause = fsl_edma_pause;
386 fsl_edma->dma_dev.device_resume = fsl_edma_resume;
387 fsl_edma->dma_dev.device_terminate_all = fsl_edma_terminate_all;
388 fsl_edma->dma_dev.device_synchronize = fsl_edma_synchronize;
389 fsl_edma->dma_dev.device_issue_pending = fsl_edma_issue_pending;
391 fsl_edma->dma_dev.src_addr_widths = FSL_EDMA_BUSWIDTHS;
392 fsl_edma->dma_dev.dst_addr_widths = FSL_EDMA_BUSWIDTHS;
393 fsl_edma->dma_dev.directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
395 platform_set_drvdata(pdev, fsl_edma);
397 ret = dma_async_device_register(&fsl_edma->dma_dev);
401 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
405 ret = of_dma_controller_register(np, fsl_edma_xlate, fsl_edma);
409 dma_async_device_unregister(&fsl_edma->dma_dev);
410 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
415 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);
423 struct fsl_edma_engine *fsl_edma = platform_get_drvdata(pdev);
425 fsl_edma_irq_exit(pdev, fsl_edma);
426 fsl_edma_cleanup_vchan(&fsl_edma->dma_dev);
428 dma_async_device_unregister(&fsl_edma->dma_dev);
429 fsl_disable_clocks(fsl_edma, fsl_edma->drvdata->dmamuxs);
436 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
441 for (i = 0; i < fsl_edma->n_chans; i++) {
442 fsl_chan = &fsl_edma->chans[i];
460 struct fsl_edma_engine *fsl_edma = dev_get_drvdata(dev);
462 struct edma_regs *regs = &fsl_edma->regs;
465 for (i = 0; i < fsl_edma->n_chans; i++) {
466 fsl_chan = &fsl_edma->chans[i];
468 edma_writew(fsl_edma, 0x0, ®s->tcd[i].csr);
473 edma_writel(fsl_edma, EDMA_CR_ERGA | EDMA_CR_ERCA, regs->cr);