Lines Matching refs:edmac
219 static inline struct device *chan2dev(struct ep93xx_dma_chan *edmac)
221 return &edmac->chan.dev->device;
231 * @edmac: channel
238 * Called with @edmac->lock held and interrupts disabled.
240 static void ep93xx_dma_set_active(struct ep93xx_dma_chan *edmac,
243 BUG_ON(!list_empty(&edmac->active));
245 list_add_tail(&desc->node, &edmac->active);
247 /* Flatten the @desc->tx_list chain into @edmac->active list */
261 list_move_tail(&d->node, &edmac->active);
265 /* Called with @edmac->lock held and interrupts disabled */
267 ep93xx_dma_get_active(struct ep93xx_dma_chan *edmac)
269 return list_first_entry_or_null(&edmac->active,
275 * @edmac: channel
277 * Function advances active descriptor to the next in the @edmac->active and
283 * Called with @edmac->lock held and interrupts disabled.
285 static bool ep93xx_dma_advance_active(struct ep93xx_dma_chan *edmac)
289 list_rotate_left(&edmac->active);
291 if (test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags))
294 desc = ep93xx_dma_get_active(edmac);
309 static void m2p_set_control(struct ep93xx_dma_chan *edmac, u32 control)
311 writel(control, edmac->regs + M2P_CONTROL);
316 readl(edmac->regs + M2P_CONTROL);
319 static int m2p_hw_setup(struct ep93xx_dma_chan *edmac)
321 struct ep93xx_dma_data *data = edmac->chan.private;
324 writel(data->port & 0xf, edmac->regs + M2P_PPALLOC);
328 m2p_set_control(edmac, control);
330 edmac->buffer = 0;
335 static inline u32 m2p_channel_state(struct ep93xx_dma_chan *edmac)
337 return (readl(edmac->regs + M2P_STATUS) >> 4) & 0x3;
340 static void m2p_hw_synchronize(struct ep93xx_dma_chan *edmac)
345 spin_lock_irqsave(&edmac->lock, flags);
346 control = readl(edmac->regs + M2P_CONTROL);
348 m2p_set_control(edmac, control);
349 spin_unlock_irqrestore(&edmac->lock, flags);
351 while (m2p_channel_state(edmac) >= M2P_STATE_ON)
355 static void m2p_hw_shutdown(struct ep93xx_dma_chan *edmac)
357 m2p_set_control(edmac, 0);
359 while (m2p_channel_state(edmac) != M2P_STATE_IDLE)
360 dev_warn(chan2dev(edmac), "M2P: Not yet IDLE\n");
363 static void m2p_fill_desc(struct ep93xx_dma_chan *edmac)
368 desc = ep93xx_dma_get_active(edmac);
370 dev_warn(chan2dev(edmac), "M2P: empty descriptor list\n");
374 if (ep93xx_dma_chan_direction(&edmac->chan) == DMA_MEM_TO_DEV)
379 if (edmac->buffer == 0) {
380 writel(desc->size, edmac->regs + M2P_MAXCNT0);
381 writel(bus_addr, edmac->regs + M2P_BASE0);
383 writel(desc->size, edmac->regs + M2P_MAXCNT1);
384 writel(bus_addr, edmac->regs + M2P_BASE1);
387 edmac->buffer ^= 1;
390 static void m2p_hw_submit(struct ep93xx_dma_chan *edmac)
392 u32 control = readl(edmac->regs + M2P_CONTROL);
394 m2p_fill_desc(edmac);
397 if (ep93xx_dma_advance_active(edmac)) {
398 m2p_fill_desc(edmac);
402 m2p_set_control(edmac, control);
405 static int m2p_hw_interrupt(struct ep93xx_dma_chan *edmac)
407 u32 irq_status = readl(edmac->regs + M2P_INTERRUPT);
411 struct ep93xx_dma_desc *desc = ep93xx_dma_get_active(edmac);
414 writel(1, edmac->regs + M2P_INTERRUPT);
424 dev_err(chan2dev(edmac),
442 if (ep93xx_dma_advance_active(edmac)) {
443 m2p_fill_desc(edmac);
448 control = readl(edmac->regs + M2P_CONTROL);
450 m2p_set_control(edmac, control);
459 static int m2m_hw_setup(struct ep93xx_dma_chan *edmac)
461 const struct ep93xx_dma_data *data = edmac->chan.private;
466 writel(control, edmac->regs + M2M_CONTROL);
516 writel(control, edmac->regs + M2M_CONTROL);
520 static void m2m_hw_shutdown(struct ep93xx_dma_chan *edmac)
523 writel(0, edmac->regs + M2M_CONTROL);
526 static void m2m_fill_desc(struct ep93xx_dma_chan *edmac)
530 desc = ep93xx_dma_get_active(edmac);
532 dev_warn(chan2dev(edmac), "M2M: empty descriptor list\n");
536 if (edmac->buffer == 0) {
537 writel(desc->src_addr, edmac->regs + M2M_SAR_BASE0);
538 writel(desc->dst_addr, edmac->regs + M2M_DAR_BASE0);
539 writel(desc->size, edmac->regs + M2M_BCR0);
541 writel(desc->src_addr, edmac->regs + M2M_SAR_BASE1);
542 writel(desc->dst_addr, edmac->regs + M2M_DAR_BASE1);
543 writel(desc->size, edmac->regs + M2M_BCR1);
546 edmac->buffer ^= 1;
549 static void m2m_hw_submit(struct ep93xx_dma_chan *edmac)
551 struct ep93xx_dma_data *data = edmac->chan.private;
552 u32 control = readl(edmac->regs + M2M_CONTROL);
560 control |= edmac->runtime_ctrl;
562 m2m_fill_desc(edmac);
565 if (ep93xx_dma_advance_active(edmac)) {
566 m2m_fill_desc(edmac);
575 writel(control, edmac->regs + M2M_CONTROL);
583 writel(control, edmac->regs + M2M_CONTROL);
597 static int m2m_hw_interrupt(struct ep93xx_dma_chan *edmac)
599 u32 status = readl(edmac->regs + M2M_STATUS);
608 if (!(readl(edmac->regs + M2M_INTERRUPT) & M2M_INTERRUPT_MASK))
613 writel(0, edmac->regs + M2M_INTERRUPT);
620 desc = ep93xx_dma_get_active(edmac);
637 if (ep93xx_dma_advance_active(edmac)) {
638 m2m_fill_desc(edmac);
639 if (done && !edmac->chan.private) {
641 control = readl(edmac->regs + M2M_CONTROL);
643 writel(control, edmac->regs + M2M_CONTROL);
659 control = readl(edmac->regs + M2M_CONTROL);
662 writel(control, edmac->regs + M2M_CONTROL);
677 ep93xx_dma_desc_get(struct ep93xx_dma_chan *edmac)
683 spin_lock_irqsave(&edmac->lock, flags);
684 list_for_each_entry_safe(desc, _desc, &edmac->free_list, node) {
701 spin_unlock_irqrestore(&edmac->lock, flags);
705 static void ep93xx_dma_desc_put(struct ep93xx_dma_chan *edmac,
711 spin_lock_irqsave(&edmac->lock, flags);
712 list_splice_init(&desc->tx_list, &edmac->free_list);
713 list_add(&desc->node, &edmac->free_list);
714 spin_unlock_irqrestore(&edmac->lock, flags);
720 * @edmac: channel
723 * function takes the next queued transaction from the @edmac->queue and
726 static void ep93xx_dma_advance_work(struct ep93xx_dma_chan *edmac)
731 spin_lock_irqsave(&edmac->lock, flags);
732 if (!list_empty(&edmac->active) || list_empty(&edmac->queue)) {
733 spin_unlock_irqrestore(&edmac->lock, flags);
738 new = list_first_entry(&edmac->queue, struct ep93xx_dma_desc, node);
741 ep93xx_dma_set_active(edmac, new);
744 edmac->edma->hw_submit(edmac);
745 spin_unlock_irqrestore(&edmac->lock, flags);
750 struct ep93xx_dma_chan *edmac = from_tasklet(edmac, t, tasklet);
756 spin_lock_irq(&edmac->lock);
762 desc = ep93xx_dma_get_active(edmac);
766 if (!test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags))
768 list_splice_init(&edmac->active, &list);
772 spin_unlock_irq(&edmac->lock);
775 ep93xx_dma_advance_work(edmac);
780 ep93xx_dma_desc_put(edmac, desc);
788 struct ep93xx_dma_chan *edmac = dev_id;
792 spin_lock(&edmac->lock);
794 desc = ep93xx_dma_get_active(edmac);
796 dev_warn(chan2dev(edmac),
798 spin_unlock(&edmac->lock);
802 switch (edmac->edma->hw_interrupt(edmac)) {
805 tasklet_schedule(&edmac->tasklet);
809 if (test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags))
810 tasklet_schedule(&edmac->tasklet);
814 dev_warn(chan2dev(edmac), "unknown interrupt!\n");
819 spin_unlock(&edmac->lock);
833 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(tx->chan);
838 spin_lock_irqsave(&edmac->lock, flags);
848 if (list_empty(&edmac->active)) {
849 ep93xx_dma_set_active(edmac, desc);
850 edmac->edma->hw_submit(edmac);
852 list_add_tail(&desc->node, &edmac->queue);
855 spin_unlock_irqrestore(&edmac->lock, flags);
869 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
875 if (!edmac->edma->m2m) {
900 ret = clk_enable(edmac->clk);
904 ret = request_irq(edmac->irq, ep93xx_dma_interrupt, 0, name, edmac);
908 spin_lock_irq(&edmac->lock);
909 dma_cookie_init(&edmac->chan);
910 ret = edmac->edma->hw_setup(edmac);
911 spin_unlock_irq(&edmac->lock);
921 dev_warn(chan2dev(edmac), "not enough descriptors\n");
931 ep93xx_dma_desc_put(edmac, desc);
937 free_irq(edmac->irq, edmac);
939 clk_disable(edmac->clk);
953 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
958 BUG_ON(!list_empty(&edmac->active));
959 BUG_ON(!list_empty(&edmac->queue));
961 spin_lock_irqsave(&edmac->lock, flags);
962 edmac->edma->hw_shutdown(edmac);
963 edmac->runtime_addr = 0;
964 edmac->runtime_ctrl = 0;
965 edmac->buffer = 0;
966 list_splice_init(&edmac->free_list, &list);
967 spin_unlock_irqrestore(&edmac->lock, flags);
972 clk_disable(edmac->clk);
973 free_irq(edmac->irq, edmac);
990 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
996 desc = ep93xx_dma_desc_get(edmac);
998 dev_warn(chan2dev(edmac), "couldn't get descriptor\n");
1019 ep93xx_dma_desc_put(edmac, first);
1039 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
1044 if (!edmac->edma->m2m && dir != ep93xx_dma_chan_direction(chan)) {
1045 dev_warn(chan2dev(edmac),
1050 if (test_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags)) {
1051 dev_warn(chan2dev(edmac),
1056 ep93xx_dma_slave_config_write(chan, dir, &edmac->slave_config);
1063 dev_warn(chan2dev(edmac), "too big transfer size %zu\n",
1068 desc = ep93xx_dma_desc_get(edmac);
1070 dev_warn(chan2dev(edmac), "couldn't get descriptor\n");
1076 desc->dst_addr = edmac->runtime_addr;
1078 desc->src_addr = edmac->runtime_addr;
1095 ep93xx_dma_desc_put(edmac, first);
1121 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
1125 if (!edmac->edma->m2m && dir != ep93xx_dma_chan_direction(chan)) {
1126 dev_warn(chan2dev(edmac),
1131 if (test_and_set_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags)) {
1132 dev_warn(chan2dev(edmac),
1138 dev_warn(chan2dev(edmac), "too big period length %zu\n",
1143 ep93xx_dma_slave_config_write(chan, dir, &edmac->slave_config);
1148 desc = ep93xx_dma_desc_get(edmac);
1150 dev_warn(chan2dev(edmac), "couldn't get descriptor\n");
1156 desc->dst_addr = edmac->runtime_addr;
1158 desc->src_addr = edmac->runtime_addr;
1175 ep93xx_dma_desc_put(edmac, first);
1193 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
1195 if (edmac->edma->hw_synchronize)
1196 edmac->edma->hw_synchronize(edmac);
1204 * @edmac->free_list and callbacks are _not_ called.
1208 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
1213 spin_lock_irqsave(&edmac->lock, flags);
1215 edmac->edma->hw_shutdown(edmac);
1216 clear_bit(EP93XX_DMA_IS_CYCLIC, &edmac->flags);
1217 list_splice_init(&edmac->active, &list);
1218 list_splice_init(&edmac->queue, &list);
1223 edmac->edma->hw_setup(edmac);
1224 spin_unlock_irqrestore(&edmac->lock, flags);
1227 ep93xx_dma_desc_put(edmac, desc);
1235 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
1237 memcpy(&edmac->slave_config, config, sizeof(*config));
1246 struct ep93xx_dma_chan *edmac = to_ep93xx_dma_chan(chan);
1251 if (!edmac->edma->m2m)
1283 spin_lock_irqsave(&edmac->lock, flags);
1284 edmac->runtime_addr = addr;
1285 edmac->runtime_ctrl = ctrl;
1286 spin_unlock_irqrestore(&edmac->lock, flags);
1338 struct ep93xx_dma_chan *edmac = &edma->channels[i];
1340 edmac->chan.device = dma_dev;
1341 edmac->regs = cdata->base;
1342 edmac->irq = cdata->irq;
1343 edmac->edma = edma;
1345 edmac->clk = clk_get(NULL, cdata->name);
1346 if (IS_ERR(edmac->clk)) {
1352 spin_lock_init(&edmac->lock);
1353 INIT_LIST_HEAD(&edmac->active);
1354 INIT_LIST_HEAD(&edmac->queue);
1355 INIT_LIST_HEAD(&edmac->free_list);
1356 tasklet_setup(&edmac->tasklet, ep93xx_dma_tasklet);
1358 list_add_tail(&edmac->chan.device_node,
1400 struct ep93xx_dma_chan *edmac = &edma->channels[i];
1401 if (!IS_ERR_OR_NULL(edmac->clk))
1402 clk_put(edmac->clk);