Lines Matching refs:val
45 axi_dma_iowrite32(struct axi_dma_chip *chip, u32 reg, u32 val)
47 iowrite32(val, chip->regs + reg);
56 axi_chan_iowrite32(struct axi_dma_chan *chan, u32 reg, u32 val)
58 iowrite32(val, chan->chan_regs + reg);
67 axi_chan_iowrite64(struct axi_dma_chan *chan, u32 reg, u64 val)
73 iowrite32(lower_32_bits(val), chan->chan_regs + reg);
74 iowrite32(upper_32_bits(val), chan->chan_regs + reg + 4);
79 u32 val;
81 val = axi_dma_ioread32(chip, DMAC_CFG);
82 val &= ~DMAC_EN_MASK;
83 axi_dma_iowrite32(chip, DMAC_CFG, val);
88 u32 val;
90 val = axi_dma_ioread32(chip, DMAC_CFG);
91 val |= DMAC_EN_MASK;
92 axi_dma_iowrite32(chip, DMAC_CFG, val);
97 u32 val;
99 val = axi_dma_ioread32(chip, DMAC_CFG);
100 val &= ~INT_EN_MASK;
101 axi_dma_iowrite32(chip, DMAC_CFG, val);
106 u32 val;
108 val = axi_dma_ioread32(chip, DMAC_CFG);
109 val |= INT_EN_MASK;
110 axi_dma_iowrite32(chip, DMAC_CFG, val);
115 u32 val;
120 val = axi_chan_ioread32(chan, CH_INTSTATUS_ENA);
121 val &= ~irq_mask;
122 axi_chan_iowrite32(chan, CH_INTSTATUS_ENA, val);
148 u32 val;
150 val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
151 val &= ~(BIT(chan->id) << DMAC_CHAN_EN_SHIFT);
152 val |= BIT(chan->id) << DMAC_CHAN_EN_WE_SHIFT;
153 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
158 u32 val;
160 val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
161 val |= BIT(chan->id) << DMAC_CHAN_EN_SHIFT |
163 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
168 u32 val;
170 val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
172 return !!(val & (BIT(chan->id) << DMAC_CHAN_EN_SHIFT));
383 u32 val;
385 val = le32_to_cpu(desc->lli.ctl_hi);
386 val |= CH_CTL_H_LLI_LAST;
387 desc->lli.ctl_hi = cpu_to_le32(val);
402 u32 val;
405 val = le32_to_cpu(desc->lli.ctl_lo);
406 val &= ~CH_CTL_L_SRC_MAST;
407 desc->lli.ctl_lo = cpu_to_le32(val);
412 u32 val;
415 val = le32_to_cpu(desc->lli.ctl_lo);
417 val |= CH_CTL_L_DST_MAST;
419 val &= ~CH_CTL_L_DST_MAST;
421 desc->lli.ctl_lo = cpu_to_le32(val);
659 u32 val;
663 val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
664 val |= BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT |
666 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);
687 u32 val;
689 val = axi_dma_ioread32(chan->chip, DMAC_CHEN);
690 val &= ~(BIT(chan->id) << DMAC_CHAN_SUSP_SHIFT);
691 val |= (BIT(chan->id) << DMAC_CHAN_SUSP_WE_SHIFT);
692 axi_dma_iowrite32(chan->chip, DMAC_CHEN, val);