Lines Matching refs:dw
26 #include "dw-axi-dmac.h"
179 for (i = 0; i < chip->dw->hdata->nr_channels; i++) {
180 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
181 axi_chan_disable(&chip->dw->chan[i]);
188 u32 max_width = chan->chip->dw->hdata->m_data_width;
200 struct dw_axi_dma *dw = chan->chip->dw;
204 desc = dma_pool_zalloc(dw->desc_pool, GFP_NOWAIT, &phys);
222 struct dw_axi_dma *dw = chan->chip->dw;
228 dma_pool_free(dw->desc_pool, child, child->vd.tx.phys);
232 dma_pool_free(dw->desc_pool, desc, desc->vd.tx.phys);
275 u32 priority = chan->chip->dw->hdata->priority[chan->id];
416 if (desc->chan->chip->dw->hdata->nr_masters > 1)
437 max_block_ts = chan->chip->dw->hdata->block_size[chan->id];
469 if (chan->chip->dw->hdata->restrict_axi_burst_len) {
470 u32 burst_len = chan->chip->dw->hdata->axi_rw_burst_len;
604 struct dw_axi_dma *dw = chip->dw;
613 for (i = 0; i < dw->hdata->nr_channels; i++) {
614 chan = &dw->chan[i];
767 chip->dw->hdata->nr_channels = tmp;
775 chip->dw->hdata->nr_masters = tmp;
783 chip->dw->hdata->m_data_width = tmp;
786 chip->dw->hdata->nr_channels);
789 for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) {
793 chip->dw->hdata->block_size[tmp] = carr[tmp];
797 chip->dw->hdata->nr_channels);
801 for (tmp = 0; tmp < chip->dw->hdata->nr_channels; tmp++) {
802 if (carr[tmp] >= chip->dw->hdata->nr_channels)
805 chip->dw->hdata->priority[tmp] = carr[tmp];
816 chip->dw->hdata->restrict_axi_burst_len = true;
817 chip->dw->hdata->axi_rw_burst_len = tmp - 1;
827 struct dw_axi_dma *dw;
836 dw = devm_kzalloc(&pdev->dev, sizeof(*dw), GFP_KERNEL);
837 if (!dw)
844 chip->dw = dw;
846 chip->dw->hdata = hdata;
869 dw->chan = devm_kcalloc(chip->dev, hdata->nr_channels,
870 sizeof(*dw->chan), GFP_KERNEL);
871 if (!dw->chan)
880 dw->desc_pool = dmam_pool_create(KBUILD_MODNAME, chip->dev,
882 if (!dw->desc_pool) {
887 INIT_LIST_HEAD(&dw->dma.channels);
889 struct axi_dma_chan *chan = &dw->chan[i];
897 vchan_init(&chan->vc, &dw->dma);
901 dma_cap_set(DMA_MEMCPY, dw->dma.cap_mask);
904 dw->dma.chancnt = hdata->nr_channels;
905 dw->dma.src_addr_widths = AXI_DMA_BUSWIDTHS;
906 dw->dma.dst_addr_widths = AXI_DMA_BUSWIDTHS;
907 dw->dma.directions = BIT(DMA_MEM_TO_MEM);
908 dw->dma.residue_granularity = DMA_RESIDUE_GRANULARITY_DESCRIPTOR;
910 dw->dma.dev = chip->dev;
911 dw->dma.device_tx_status = dma_chan_tx_status;
912 dw->dma.device_issue_pending = dma_chan_issue_pending;
913 dw->dma.device_terminate_all = dma_chan_terminate_all;
914 dw->dma.device_pause = dma_chan_pause;
915 dw->dma.device_resume = dma_chan_resume;
917 dw->dma.device_alloc_chan_resources = dma_chan_alloc_chan_resources;
918 dw->dma.device_free_chan_resources = dma_chan_free_chan_resources;
920 dw->dma.device_prep_dma_memcpy = dma_chan_prep_dma_memcpy;
940 ret = dmaenginem_async_device_register(&dw->dma);
945 dw->hdata->nr_channels);
958 struct dw_axi_dma *dw = chip->dw;
966 for (i = 0; i < dw->hdata->nr_channels; i++) {
967 axi_chan_disable(&chip->dw->chan[i]);
968 axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
977 list_for_each_entry_safe(chan, _chan, &dw->dma.channels,