Lines Matching refs:jzdma
182 static inline uint32_t jz4780_dma_chn_readl(struct jz4780_dma_dev *jzdma,
185 return readl(jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn));
188 static inline void jz4780_dma_chn_writel(struct jz4780_dma_dev *jzdma,
191 writel(val, jzdma->chn_base + reg + JZ_DMA_REG_CHAN(chn));
194 static inline uint32_t jz4780_dma_ctrl_readl(struct jz4780_dma_dev *jzdma,
197 return readl(jzdma->ctrl_base + reg);
200 static inline void jz4780_dma_ctrl_writel(struct jz4780_dma_dev *jzdma,
203 writel(val, jzdma->ctrl_base + reg);
206 static inline void jz4780_dma_chan_enable(struct jz4780_dma_dev *jzdma,
209 if (jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) {
212 if (jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC)
217 jz4780_dma_ctrl_writel(jzdma, reg, BIT(chn));
221 static inline void jz4780_dma_chan_disable(struct jz4780_dma_dev *jzdma,
224 if ((jzdma->soc_data->flags & JZ_SOC_DATA_PER_CHAN_PM) &&
225 !(jzdma->soc_data->flags & JZ_SOC_DATA_NO_DCKES_DCKEC))
226 jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DCKEC, BIT(chn));
266 struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
278 else if (ord > jzdma->soc_data->transfer_ord_max)
279 ord = jzdma->soc_data->transfer_ord_max;
359 struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
381 !(jzdma->soc_data->flags & JZ_SOC_DATA_BREAK_LINKS)) {
480 struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
524 jz4780_dma_chan_enable(jzdma, jzchan->id);
527 jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);
530 jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DRT,
539 jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DTC,
545 jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DDA, desc_phys);
546 jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DDRS, BIT(jzchan->id));
549 jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS,
569 struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
576 jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);
582 jz4780_dma_chan_disable(jzdma, jzchan->id);
595 struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
598 jz4780_dma_chan_disable(jzdma, jzchan->id);
619 struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
627 count += jz4780_dma_chn_readl(jzdma, jzchan->id,
668 static bool jz4780_dma_chan_irq(struct jz4780_dma_dev *jzdma,
671 const unsigned int soc_flags = jzdma->soc_data->flags;
678 dcs = jz4780_dma_chn_readl(jzdma, jzchan->id, JZ_DMA_REG_DCS);
679 jz4780_dma_chn_writel(jzdma, jzchan->id, JZ_DMA_REG_DCS, 0);
710 jz4780_dma_chn_writel(jzdma, jzchan->id,
727 struct jz4780_dma_dev *jzdma = data;
728 unsigned int nb_channels = jzdma->soc_data->nb_channels;
733 pending = jz4780_dma_ctrl_readl(jzdma, JZ_DMA_REG_DIRQP);
736 if (jz4780_dma_chan_irq(jzdma, &jzdma->chan[i]))
741 dmac = jz4780_dma_ctrl_readl(jzdma, JZ_DMA_REG_DMAC);
743 jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMAC, dmac);
746 jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DIRQP, pending);
780 struct jz4780_dma_dev *jzdma = jz4780_dma_chan_parent(jzchan);
787 } else if (jzdma->chan_reserved & BIT(jzchan->id)) {
799 struct jz4780_dma_dev *jzdma = ofdma->of_dma_data;
800 dma_cap_mask_t mask = jzdma->dma_device.cap_mask;
810 if (data.channel >= jzdma->soc_data->nb_channels) {
811 dev_err(jzdma->dma_device.dev,
818 if (!(jzdma->chan_reserved & BIT(data.channel))) {
819 dev_err(jzdma->dma_device.dev,
825 jzdma->chan[data.channel].transfer_type = data.transfer_type;
828 &jzdma->chan[data.channel].vchan.chan);
839 struct jz4780_dma_dev *jzdma;
854 jzdma = devm_kzalloc(dev, struct_size(jzdma, chan,
856 if (!jzdma)
859 jzdma->soc_data = soc_data;
860 platform_set_drvdata(pdev, jzdma);
862 jzdma->chn_base = devm_platform_ioremap_resource(pdev, 0);
863 if (IS_ERR(jzdma->chn_base))
864 return PTR_ERR(jzdma->chn_base);
868 jzdma->ctrl_base = devm_ioremap_resource(dev, res);
869 if (IS_ERR(jzdma->ctrl_base))
870 return PTR_ERR(jzdma->ctrl_base);
877 jzdma->ctrl_base = jzdma->chn_base + JZ4780_DMA_CTRL_OFFSET;
883 jzdma->clk = devm_clk_get(dev, NULL);
884 if (IS_ERR(jzdma->clk)) {
886 ret = PTR_ERR(jzdma->clk);
890 clk_prepare_enable(jzdma->clk);
894 0, &jzdma->chan_reserved);
896 dd = &jzdma->dma_device;
924 jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMAC, JZ_DMA_DMAC_DMAE |
928 jz4780_dma_ctrl_writel(jzdma, JZ_DMA_REG_DMACP, 0);
933 jzchan = &jzdma->chan[i];
944 jzdma->irq = ret;
946 ret = request_irq(jzdma->irq, jz4780_dma_irq_handler, 0, dev_name(dev),
947 jzdma);
949 dev_err(dev, "failed to request IRQ %u!\n", jzdma->irq);
961 jzdma);
971 free_irq(jzdma->irq, jzdma);
974 clk_disable_unprepare(jzdma->clk);
980 struct jz4780_dma_dev *jzdma = platform_get_drvdata(pdev);
985 clk_disable_unprepare(jzdma->clk);
986 free_irq(jzdma->irq, jzdma);
988 for (i = 0; i < jzdma->soc_data->nb_channels; i++)
989 tasklet_kill(&jzdma->chan[i].vchan.task);