Lines Matching refs:virtbase
1282 void __iomem *virtbase;
1446 void __iomem *virtbase = cohc->base->virtbase;
1449 virtbase + COH901318_CX_CTRL +
1457 void __iomem *virtbase = cohc->base->virtbase;
1460 virtbase + COH901318_CX_CFG +
1470 void __iomem *virtbase = cohc->base->virtbase;
1474 val = readl(virtbase + COH901318_CX_CFG +
1479 writel(val, virtbase + COH901318_CX_CFG +
1489 void __iomem *virtbase = cohc->base->virtbase;
1491 BUG_ON(readl(virtbase + COH901318_CX_STAT +
1496 virtbase + COH901318_CX_SRC_ADDR +
1499 writel(lli->dst_addr, virtbase +
1503 writel(lli->link_addr, virtbase + COH901318_CX_LNK_ADDR +
1506 writel(lli->control, virtbase + COH901318_CX_CTRL +
1631 left = readl(cohc->base->virtbase +
1637 ladd = readl(cohc->base->virtbase +
1689 void __iomem *virtbase = cohc->base->virtbase;
1694 val = readl(virtbase + COH901318_CX_CFG +
1705 writel(val, virtbase + COH901318_CX_CFG +
1707 writel(val, virtbase + COH901318_CX_CFG +
1711 while (readl(virtbase + COH901318_CX_STAT+COH901318_CX_STAT_SPACING *
1716 if ((readl(virtbase + COH901318_CX_CTRL+COH901318_CX_CTRL_SPACING *
1742 val = readl(cohc->base->virtbase + COH901318_CX_CFG +
1747 writel(val, cohc->base->virtbase + COH901318_CX_CFG +
1805 void __iomem *virtbase = cohc->base->virtbase;
1814 writel(1 << channel, virtbase + COH901318_BE_INT_CLEAR1);
1815 writel(1 << channel, virtbase + COH901318_TC_INT_CLEAR1);
1817 writel(1 << (channel - 32), virtbase +
1819 writel(1 << (channel - 32), virtbase +
1989 void __iomem *virtbase = base->virtbase;
1991 status1 = readl(virtbase + COH901318_INT_STATUS1);
1992 status2 = readl(virtbase + COH901318_INT_STATUS2);
2014 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS1)) {
2019 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR1);
2022 if (unlikely(!test_bit(i, virtbase +
2028 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
2031 if (!(readl(virtbase + COH901318_CX_STAT +
2041 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR1);
2060 if (test_bit(i, virtbase + COH901318_BE_INT_STATUS2)) {
2065 __set_bit(i, virtbase + COH901318_BE_INT_CLEAR2);
2068 if (unlikely(!test_bit(i, virtbase +
2073 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
2077 if (!(readl(virtbase + COH901318_CX_STAT +
2086 __set_bit(i, virtbase + COH901318_TC_INT_CLEAR2);
2102 void __iomem *virtbase = cohc->base->virtbase;
2110 writel(1 << cohc->id, virtbase + COH901318_BE_INT_CLEAR1);
2111 writel(1 << cohc->id, virtbase + COH901318_TC_INT_CLEAR1);
2113 writel(1 << (cohc->id - 32), virtbase +
2115 writel(1 << (cohc->id - 32), virtbase +
2181 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CFG +
2183 writel(0x00000000U, cohc->base->virtbase + COH901318_CX_CTRL +
2654 base->virtbase = devm_ioremap(&pdev->dev, io->start, resource_size(io));
2655 if (!base->virtbase)
2738 base->virtbase);