Lines Matching refs:pl08x
64 #include <linux/amba/pl08x.h>
391 static void pl08x_write_lli(struct pl08x_driver_data *pl08x,
394 if (pl08x->vd->pl080s)
395 dev_vdbg(&pl08x->adev->dev,
402 dev_vdbg(&pl08x->adev->dev,
463 switch (pl08x->pd->memcpy_burst_size) {
500 if (pl08x->pd->memcpy_prot_buff)
502 if (pl08x->pd->memcpy_prot_cache)
514 if (pl08x->vd->pl080s)
529 struct pl08x_driver_data *pl08x = plchan->host;
543 pl08x_write_lli(pl08x, phychan, &txd->llis_va[0], txd->ccfg);
547 while (readl(pl08x->base + PL080_EN_CHAN) & BIT(phychan->id))
607 pr_err("pl08x: channel%u timeout waiting for pause\n", ch->id);
634 static void pl08x_terminate_phy_chan(struct pl08x_driver_data *pl08x,
656 pl08x->base + PL080_ERR_CLEAR);
657 writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR);
667 writel(BIT(ch->id), pl08x->base + PL080_ERR_CLEAR);
668 writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR);
755 struct pl08x_driver_data *pl08x = plchan->host;
785 llis_max_words = pl08x->lli_words * MAX_NUM_TSFR_LLIS;
797 for (; llis_va < llis_va_limit; llis_va += pl08x->lli_words) {
818 pl08x_get_phy_channel(struct pl08x_driver_data *pl08x,
825 for (i = 0; i < pl08x->vd->channels; i++) {
826 ch = &pl08x->phy_chans[i];
839 if (i == pl08x->vd->channels) {
848 static inline void pl08x_put_phy_channel(struct pl08x_driver_data *pl08x,
861 struct pl08x_driver_data *pl08x = plchan->host;
864 ch = pl08x_get_phy_channel(pl08x, plchan);
866 dev_dbg(&pl08x->adev->dev, "no physical channel available for xfer on %s\n", plchan->name);
872 dev_dbg(&pl08x->adev->dev, "allocated physical channel %d for xfer on %s\n",
883 struct pl08x_driver_data *pl08x = plchan->host;
885 dev_dbg(&pl08x->adev->dev, "reassigned physical channel %d for xfer on %s\n",
905 struct pl08x_driver_data *pl08x = plchan->host;
917 list_for_each_entry(p, &pl08x->memcpy.channels, vc.chan.device_node)
924 if (!next && pl08x->has_slave) {
925 list_for_each_entry(p, &pl08x->slave.channels, vc.chan.device_node)
934 pl08x_terminate_phy_chan(pl08x, plchan->phychan);
955 pl08x_put_phy_channel(pl08x, plchan->phychan);
967 pl08x_get_bytes_for_lli(struct pl08x_driver_data *pl08x,
973 if (pl08x->vd->ftdmac020) {
1003 static inline u32 pl08x_lli_control_bits(struct pl08x_driver_data *pl08x,
1015 if (pl08x->vd->ftdmac020) {
1123 static void pl08x_choose_master_bus(struct pl08x_driver_data *pl08x,
1136 if (pl08x->vd->ftdmac020) {
1168 static void pl08x_fill_lli_for_desc(struct pl08x_driver_data *pl08x,
1172 u32 offset = num_llis * pl08x->lli_words;
1179 offset += pl08x->lli_words;
1186 if (pl08x->vd->pl080s)
1189 if (pl08x->vd->ftdmac020) {
1205 static inline void prep_byte_width_lli(struct pl08x_driver_data *pl08x,
1209 *cctl = pl08x_lli_control_bits(pl08x, *cctl, 1, 1, len);
1210 pl08x_fill_lli_for_desc(pl08x, bd, num_llis, len, *cctl, len);
1215 static void pl08x_dump_lli(struct pl08x_driver_data *pl08x,
1220 if (pl08x->vd->pl080s) {
1221 dev_vdbg(&pl08x->adev->dev,
1225 dev_vdbg(&pl08x->adev->dev,
1231 llis_va += pl08x->lli_words;
1234 dev_vdbg(&pl08x->adev->dev,
1238 dev_vdbg(&pl08x->adev->dev,
1243 llis_va += pl08x->lli_words;
1248 static inline void pl08x_dump_lli(struct pl08x_driver_data *pl08x,
1257 static int pl08x_fill_llis_for_desc(struct pl08x_driver_data *pl08x,
1268 txd->llis_va = dma_pool_alloc(pl08x->pool, GFP_NOWAIT, &txd->llis_bus);
1270 dev_err(&pl08x->adev->dev, "%s no memory for llis\n", __func__);
1275 bd.lli_bus = (pl08x->lli_buses & PL08X_AHB2) ? PL080_LLI_LM_AHB2 : 0;
1279 bd.srcbus.maxwidth = pl08x_get_bytes_for_lli(pl08x, cctl, true);
1282 bd.dstbus.maxwidth = pl08x_get_bytes_for_lli(pl08x, cctl, false);
1294 pl08x_choose_master_bus(pl08x, &bd, &mbus, &sbus, cctl);
1296 dev_vdbg(&pl08x->adev->dev,
1305 dev_vdbg(&pl08x->adev->dev, "mbus=%s sbus=%s\n",
1334 if (pl08x->vd->ftdmac020)
1341 dev_err(&pl08x->adev->dev, "%s sg len can't be zero",
1348 dev_err(&pl08x->adev->dev,
1355 cctl = pl08x_lli_control_bits(pl08x, cctl,
1358 pl08x_fill_lli_for_desc(pl08x, &bd, num_llis++,
1378 dev_vdbg(&pl08x->adev->dev,
1381 prep_byte_width_lli(pl08x, &bd, &cctl, early_bytes,
1391 dev_dbg(&pl08x->adev->dev,
1403 pl08x->vd->max_transfer_size;
1404 dev_vdbg(&pl08x->adev->dev,
1431 dev_vdbg(&pl08x->adev->dev,
1436 cctl = pl08x_lli_control_bits(pl08x, cctl,
1439 pl08x_fill_lli_for_desc(pl08x, &bd, num_llis++,
1448 dev_vdbg(&pl08x->adev->dev,
1451 prep_byte_width_lli(pl08x, &bd, &cctl,
1457 dev_err(&pl08x->adev->dev,
1464 dev_err(&pl08x->adev->dev,
1472 last_lli = llis_va + (num_llis - 1) * pl08x->lli_words;
1481 if (pl08x->vd->ftdmac020)
1487 pl08x_dump_lli(pl08x, llis_va, num_llis);
1492 static void pl08x_free_txd(struct pl08x_driver_data *pl08x,
1498 dma_pool_free(pl08x->pool, txd->llis_va, txd->llis_bus);
1520 static void pl08x_free_txd_list(struct pl08x_driver_data *pl08x,
1761 static u32 pl08x_memcpy_cctl(struct pl08x_driver_data *pl08x)
1766 switch (pl08x->pd->memcpy_burst_size) {
1768 dev_err(&pl08x->adev->dev,
1805 switch (pl08x->pd->memcpy_bus_width) {
1807 dev_err(&pl08x->adev->dev,
1825 if (pl08x->pd->memcpy_prot_buff)
1827 if (pl08x->pd->memcpy_prot_cache)
1836 if (pl08x->vd->dualmaster)
1838 pl08x->mem_buses,
1839 pl08x->mem_buses);
1844 static u32 pl08x_ftdmac020_memcpy_cctl(struct pl08x_driver_data *pl08x)
1849 switch (pl08x->pd->memcpy_bus_width) {
1851 dev_err(&pl08x->adev->dev,
1878 if (pl08x->vd->dualmaster)
1880 pl08x->mem_buses,
1881 pl08x->mem_buses);
1894 struct pl08x_driver_data *pl08x = plchan->host;
1901 dev_err(&pl08x->adev->dev,
1908 pl08x_free_txd(pl08x, txd);
1916 if (pl08x->vd->ftdmac020) {
1919 txd->cctl = pl08x_ftdmac020_memcpy_cctl(pl08x);
1924 txd->cctl = pl08x_memcpy_cctl(pl08x);
1929 pl08x_free_txd(pl08x, txd);
1942 struct pl08x_driver_data *pl08x = plchan->host;
1951 dev_err(&pl08x->adev->dev, "%s no txd\n", __func__);
1965 src_buses = pl08x->mem_buses;
1973 dst_buses = pl08x->mem_buses;
1975 pl08x_free_txd(pl08x, txd);
1976 dev_err(&pl08x->adev->dev,
1983 pl08x_free_txd(pl08x, txd);
1984 dev_err(&pl08x->adev->dev,
2004 pl08x_free_txd(pl08x, txd);
2005 dev_dbg(&pl08x->adev->dev,
2011 dev_dbg(&pl08x->adev->dev, "allocated DMA request signal %d for xfer on %s\n",
2055 struct pl08x_driver_data *pl08x = plchan->host;
2061 dev_dbg(&pl08x->adev->dev, "%s prepare transaction of %d bytes from %s\n",
2074 pl08x_free_txd(pl08x, txd);
2075 dev_err(&pl08x->adev->dev, "%s no mem for pl080 sg\n",
2084 pl08x_free_txd(pl08x, txd);
2097 struct pl08x_driver_data *pl08x = plchan->host;
2102 dev_dbg(&pl08x->adev->dev,
2119 pl08x_free_txd(pl08x, txd);
2127 pl08x_free_txd(pl08x, txd);
2138 struct pl08x_driver_data *pl08x = plchan->host;
2148 if (config->device_fc && pl08x->vd->pl080s) {
2149 dev_err(&pl08x->adev->dev,
2163 struct pl08x_driver_data *pl08x = plchan->host;
2187 pl08x_free_txd_list(pl08x, plchan);
2279 static void pl08x_ensure_on(struct pl08x_driver_data *pl08x)
2282 if (pl08x->vd->nomadik)
2285 if (pl08x->vd->ftdmac020) {
2286 writel(PL080_CONFIG_ENABLE, pl08x->base + FTDMAC020_CSR);
2289 writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG);
2294 struct pl08x_driver_data *pl08x = dev;
2298 err = readl(pl08x->base + PL080_ERR_STATUS);
2300 dev_err(&pl08x->adev->dev, "%s error interrupt, register value 0x%08x\n",
2302 writel(err, pl08x->base + PL080_ERR_CLEAR);
2304 tc = readl(pl08x->base + PL080_TC_STATUS);
2306 writel(tc, pl08x->base + PL080_TC_CLEAR);
2311 for (i = 0; i < pl08x->vd->channels; i++) {
2314 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
2319 dev_err(&pl08x->adev->dev,
2369 static int pl08x_dma_init_virtual_channels(struct pl08x_driver_data *pl08x,
2387 chan->host = pl08x;
2392 chan->cd = &pl08x->pd->slave_channels[i];
2407 chan->cd->periph_buses = pl08x->pd->mem_buses;
2415 dev_dbg(&pl08x->adev->dev,
2422 dev_info(&pl08x->adev->dev, "initialized %d virtual %s channels\n",
2459 struct pl08x_driver_data *pl08x = s->private;
2468 for (i = 0; i < pl08x->vd->channels; i++) {
2471 ch = &pl08x->phy_chans[i];
2487 list_for_each_entry(chan, &pl08x->memcpy.channels, vc.chan.device_node) {
2492 if (pl08x->has_slave) {
2496 list_for_each_entry(chan, &pl08x->slave.channels,
2508 static void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
2511 debugfs_create_file(dev_name(&pl08x->adev->dev), S_IFREG | S_IRUGO,
2512 NULL, pl08x, &pl08x_debugfs_fops);
2516 static inline void init_pl08x_debugfs(struct pl08x_driver_data *pl08x)
2522 static struct dma_chan *pl08x_find_chan_id(struct pl08x_driver_data *pl08x,
2528 if (!pl08x->has_slave)
2531 list_for_each_entry(chan, &pl08x->slave.channels, vc.chan.device_node) {
2542 struct pl08x_driver_data *pl08x = ofdma->of_dma_data;
2546 if (!pl08x)
2550 dev_err(&pl08x->adev->dev,
2555 dma_chan = pl08x_find_chan_id(pl08x, dma_spec->args[0]);
2557 dev_err(&pl08x->adev->dev,
2563 dev_dbg(&pl08x->adev->dev,
2573 struct pl08x_driver_data *pl08x,
2668 if (pl08x->vd->signals) {
2670 pl08x->vd->signals,
2677 for (i = 0; i < pl08x->vd->signals; i++) {
2684 pd->num_slave_channels = pl08x->vd->signals;
2687 pl08x->pd = pd;
2690 pl08x);
2694 struct pl08x_driver_data *pl08x,
2703 struct pl08x_driver_data *pl08x;
2720 pl08x = kzalloc(sizeof(*pl08x), GFP_KERNEL);
2721 if (!pl08x) {
2727 pl08x->adev = adev;
2728 pl08x->vd = vd;
2730 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
2731 if (!pl08x->base) {
2739 val = readl(pl08x->base + FTDMAC020_REVISION);
2740 dev_info(&pl08x->adev->dev, "FTDMAC020 %d.%d rel %d\n",
2742 val = readl(pl08x->base + FTDMAC020_FEATURE);
2743 dev_info(&pl08x->adev->dev, "FTDMAC020 %d channels, "
2752 dev_warn(&pl08x->adev->dev,
2759 dma_cap_set(DMA_MEMCPY, pl08x->memcpy.cap_mask);
2760 pl08x->memcpy.dev = &adev->dev;
2761 pl08x->memcpy.device_free_chan_resources = pl08x_free_chan_resources;
2762 pl08x->memcpy.device_prep_dma_memcpy = pl08x_prep_dma_memcpy;
2763 pl08x->memcpy.device_prep_dma_interrupt = pl08x_prep_dma_interrupt;
2764 pl08x->memcpy.device_tx_status = pl08x_dma_tx_status;
2765 pl08x->memcpy.device_issue_pending = pl08x_issue_pending;
2766 pl08x->memcpy.device_config = pl08x_config;
2767 pl08x->memcpy.device_pause = pl08x_pause;
2768 pl08x->memcpy.device_resume = pl08x_resume;
2769 pl08x->memcpy.device_terminate_all = pl08x_terminate_all;
2770 pl08x->memcpy.device_synchronize = pl08x_synchronize;
2771 pl08x->memcpy.src_addr_widths = PL80X_DMA_BUSWIDTHS;
2772 pl08x->memcpy.dst_addr_widths = PL80X_DMA_BUSWIDTHS;
2773 pl08x->memcpy.directions = BIT(DMA_MEM_TO_MEM);
2774 pl08x->memcpy.residue_granularity = DMA_RESIDUE_GRANULARITY_SEGMENT;
2776 pl08x->memcpy.copy_align = DMAENGINE_ALIGN_4_BYTES;
2784 pl08x->has_slave = true;
2785 dma_cap_set(DMA_SLAVE, pl08x->slave.cap_mask);
2786 dma_cap_set(DMA_CYCLIC, pl08x->slave.cap_mask);
2787 pl08x->slave.dev = &adev->dev;
2788 pl08x->slave.device_free_chan_resources =
2790 pl08x->slave.device_prep_dma_interrupt =
2792 pl08x->slave.device_tx_status = pl08x_dma_tx_status;
2793 pl08x->slave.device_issue_pending = pl08x_issue_pending;
2794 pl08x->slave.device_prep_slave_sg = pl08x_prep_slave_sg;
2795 pl08x->slave.device_prep_dma_cyclic = pl08x_prep_dma_cyclic;
2796 pl08x->slave.device_config = pl08x_config;
2797 pl08x->slave.device_pause = pl08x_pause;
2798 pl08x->slave.device_resume = pl08x_resume;
2799 pl08x->slave.device_terminate_all = pl08x_terminate_all;
2800 pl08x->slave.device_synchronize = pl08x_synchronize;
2801 pl08x->slave.src_addr_widths = PL80X_DMA_BUSWIDTHS;
2802 pl08x->slave.dst_addr_widths = PL80X_DMA_BUSWIDTHS;
2803 pl08x->slave.directions =
2805 pl08x->slave.residue_granularity =
2810 pl08x->pd = dev_get_platdata(&adev->dev);
2811 if (!pl08x->pd) {
2813 ret = pl08x_of_probe(adev, pl08x, np);
2822 pl08x->slave.filter.map = pl08x->pd->slave_map;
2823 pl08x->slave.filter.mapcnt = pl08x->pd->slave_map_len;
2824 pl08x->slave.filter.fn = pl08x_filter_fn;
2828 pl08x->lli_buses = PL08X_AHB1;
2829 pl08x->mem_buses = PL08X_AHB1;
2830 if (pl08x->vd->dualmaster) {
2831 pl08x->lli_buses = pl08x->pd->lli_buses;
2832 pl08x->mem_buses = pl08x->pd->mem_buses;
2836 pl08x->lli_words = PL080S_LLI_WORDS;
2838 pl08x->lli_words = PL080_LLI_WORDS;
2839 tsfr_size = MAX_NUM_TSFR_LLIS * pl08x->lli_words * sizeof(u32);
2842 pl08x->pool = dma_pool_create(DRIVER_NAME, &pl08x->adev->dev,
2844 if (!pl08x->pool) {
2850 pl08x_ensure_on(pl08x);
2855 writel(0x0000FFFF, pl08x->base + PL080_ERR_CLEAR);
2857 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
2858 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
2861 ret = request_irq(adev->irq[0], pl08x_irq, 0, DRIVER_NAME, pl08x);
2869 pl08x->phy_chans = kzalloc((vd->channels * sizeof(*pl08x->phy_chans)),
2871 if (!pl08x->phy_chans) {
2877 struct pl08x_phy_chan *ch = &pl08x->phy_chans[i];
2880 ch->base = pl08x->base + PL080_Cx_BASE(i);
2922 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->memcpy,
2923 pl08x->vd->channels, false);
2925 dev_warn(&pl08x->adev->dev,
2932 if (pl08x->has_slave) {
2933 ret = pl08x_dma_init_virtual_channels(pl08x, &pl08x->slave,
2934 pl08x->pd->num_slave_channels, true);
2936 dev_warn(&pl08x->adev->dev,
2943 ret = dma_async_device_register(&pl08x->memcpy);
2945 dev_warn(&pl08x->adev->dev,
2951 if (pl08x->has_slave) {
2952 ret = dma_async_device_register(&pl08x->slave);
2954 dev_warn(&pl08x->adev->dev,
2961 amba_set_drvdata(adev, pl08x);
2962 init_pl08x_debugfs(pl08x);
2963 dev_info(&pl08x->adev->dev, "DMA: PL%03x%s rev%u at 0x%08llx irq %d\n",
2964 amba_part(adev), pl08x->vd->pl080s ? "s" : "", amba_rev(adev),
2970 dma_async_device_unregister(&pl08x->memcpy);
2972 if (pl08x->has_slave)
2973 pl08x_free_virtual_channels(&pl08x->slave);
2975 pl08x_free_virtual_channels(&pl08x->memcpy);
2977 kfree(pl08x->phy_chans);
2979 free_irq(adev->irq[0], pl08x);
2981 dma_pool_destroy(pl08x->pool);
2984 iounmap(pl08x->base);
2986 kfree(pl08x);