Lines Matching refs:phychan
235 * @phychan: the physical channel utilized by this channel, if there is one
249 struct pl08x_phy_chan *phychan;
392 struct pl08x_phy_chan *phychan, const u32 *lli, u32 ccfg)
398 phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST],
405 phychan->id, lli[PL080_LLI_SRC], lli[PL080_LLI_DST],
408 writel_relaxed(lli[PL080_LLI_SRC], phychan->reg_src);
409 writel_relaxed(lli[PL080_LLI_DST], phychan->reg_dst);
410 writel_relaxed(lli[PL080_LLI_LLI], phychan->reg_lli);
418 if (phychan->ftdmac020) {
424 phychan->base + FTDMAC020_CH_SIZE);
507 writel_relaxed(val, phychan->reg_control);
510 writel_relaxed(lli[PL080_LLI_CCTL], phychan->reg_control);
516 phychan->base + PL080S_CH_CONTROL2);
518 writel(ccfg, phychan->reg_config);
530 struct pl08x_phy_chan *phychan = plchan->phychan;
540 while (pl08x_phy_channel_busy(phychan))
543 pl08x_write_lli(pl08x, phychan, &txd->llis_va[0], txd->ccfg);
547 while (readl(pl08x->base + PL080_EN_CHAN) & BIT(phychan->id))
551 if (phychan->ftdmac020) {
552 val = readl(phychan->reg_config);
554 val = readl(phychan->reg_config);
556 val = readl(phychan->reg_control);
558 val = readl(phychan->reg_control);
561 phychan->reg_control);
563 val = readl(phychan->reg_config);
566 val = readl(phychan->reg_config);
568 writel(val | PL080_CONFIG_ENABLE, phychan->reg_config);
764 ch = plchan->phychan;
875 plchan->phychan = ch;
894 plchan->phychan = ch;
934 pl08x_terminate_phy_chan(pl08x, plchan->phychan);
947 pl08x_phy_reassign_start(plchan->phychan, next);
955 pl08x_put_phy_channel(pl08x, plchan->phychan);
958 plchan->phychan = NULL;
1746 if (!plchan->phychan && plchan->state != PL08X_CHAN_WAITING)
2167 if (!plchan->phychan && !plchan->at) {
2174 if (plchan->phychan) {
2211 if (!plchan->phychan && !plchan->at) {
2216 pl08x_pause_phy_chan(plchan->phychan);
2234 if (!plchan->phychan && !plchan->at) {
2239 pl08x_resume_phy_chan(plchan->phychan);
2314 struct pl08x_phy_chan *phychan = &pl08x->phy_chans[i];
2315 struct pl08x_dma_chan *plchan = phychan->serving;