Lines Matching defs:width
126 * @maxwidth: the maximum width of a transfer on this bus
127 * @buswidth: the width of this bus in bytes: 1, 2 or 4
1012 * width and size according to the parameters. The bit offsets
1117 * masters address with width requirements of transfer (by sending few byte by
1118 * byte data), slave is still not aligned, then its width will be reduced to
1278 /* Find maximum width of the source bus */
1281 /* Find maximum width of the destination bus */
1313 * - src.addr is aligned to src.width
1314 * - dst.addr is aligned to dst.width
1350 " & dst width if peripheral is flow controller",
1365 * - Less than a bus width available
1379 "%s byte width LLIs (remain 0x%08zx)\n",
1388 * - if slave is not then we must set its width down
1392 "%s set down bus width to one byte\n",
1399 * Bytes transferred = tsize * src width, not
1410 * width left
1413 size_t lli_len, tsize, width;
1424 * bus width an get a maximum remainder of the
1425 * highest bus width - 1
1427 width = max(mbus->buswidth, sbus->buswidth);
1428 lli_len = (lli_len / width) * width;
1683 static u32 pl08x_width(enum dma_slave_buswidth width)
1685 switch (width) {
1711 u32 width, burst, cctl = 0;
1713 width = pl08x_width(addr_width);
1714 if (width == ~0)
1717 cctl |= width << PL080_CONTROL_SWIDTH_SHIFT;
1718 cctl |= width << PL080_CONTROL_DWIDTH_SHIFT;
1808 "illegal bus width for memcpy, set to 8 bits\n");
1852 "illegal bus width for memcpy, set to 8 bits\n");
2642 ret = of_property_read_u32(np, "memcpy-bus-width", &val);
2644 dev_info(&adev->dev, "no memcpy bus width specified, using 8 bits\n");
2649 dev_err(&adev->dev, "illegal bus width for memcpy, set to 8 bits\n");