Lines Matching defs:val
371 unsigned int val;
375 val = readl(ch->reg_busy);
376 return !!(val & BIT(ch->id));
378 val = readl(ch->reg_config);
379 return val & PL080_CONFIG_ACTIVE;
420 u32 val = 0;
438 val |= FTDMAC020_CH_CSR_TC_MSK;
439 val |= ((llictl & FTDMAC020_LLI_SRC_WIDTH_MSK) >>
442 val |= ((llictl & FTDMAC020_LLI_DST_WIDTH_MSK) >>
445 val |= ((llictl & FTDMAC020_LLI_SRCAD_CTL_MSK) >>
448 val |= ((llictl & FTDMAC020_LLI_DSTAD_CTL_MSK) >>
452 val |= FTDMAC020_CH_CSR_SRC_SEL;
454 val |= FTDMAC020_CH_CSR_DST_SEL;
466 val |= PL080_BSIZE_1 <<
470 val |= PL080_BSIZE_4 <<
474 val |= PL080_BSIZE_8 <<
478 val |= PL080_BSIZE_16 <<
482 val |= PL080_BSIZE_32 <<
486 val |= PL080_BSIZE_64 <<
490 val |= PL080_BSIZE_128 <<
494 val |= PL080_BSIZE_256 <<
501 val |= FTDMAC020_CH_CSR_PROT2;
503 val |= FTDMAC020_CH_CSR_PROT3;
505 val |= FTDMAC020_CH_CSR_PROT1;
507 writel_relaxed(val, phychan->reg_control);
533 u32 val;
552 val = readl(phychan->reg_config);
553 while (val & FTDMAC020_CH_CFG_BUSY)
554 val = readl(phychan->reg_config);
556 val = readl(phychan->reg_control);
557 while (val & FTDMAC020_CH_CSR_EN)
558 val = readl(phychan->reg_control);
560 writel(val | FTDMAC020_CH_CSR_EN,
563 val = readl(phychan->reg_config);
564 while ((val & PL080_CONFIG_ACTIVE) ||
565 (val & PL080_CONFIG_ENABLE))
566 val = readl(phychan->reg_config);
568 writel(val | PL080_CONFIG_ENABLE, phychan->reg_config);
584 u32 val;
589 val = readl(ch->reg_control);
590 val &= ~FTDMAC020_CH_CSR_EN;
591 writel(val, ch->reg_control);
596 val = readl(ch->reg_config);
597 val |= PL080_CONFIG_HALT;
598 writel(val, ch->reg_config);
612 u32 val;
616 val = readl(ch->reg_control);
617 val |= FTDMAC020_CH_CSR_EN;
618 writel(val, ch->reg_control);
623 val = readl(ch->reg_config);
624 val &= ~PL080_CONFIG_HALT;
625 writel(val, ch->reg_config);
637 u32 val;
642 val = readl(ch->reg_config);
643 val |= (FTDMAC020_CH_CFG_INT_ABT_MASK |
646 writel(val, ch->reg_config);
649 val = readl(ch->reg_control);
650 val &= ~FTDMAC020_CH_CSR_EN;
651 val |= FTDMAC020_CH_CSR_ABT;
652 writel(val, ch->reg_control);
662 val = readl(ch->reg_config);
663 val &= ~(PL080_CONFIG_ENABLE | PL080_CONFIG_ERR_IRQ_MASK |
665 writel(val, ch->reg_config);
673 u32 val;
679 val = readl(ch->reg_control);
680 val &= FTDMAC020_CH_CSR_SRC_WIDTH_MSK;
681 val >>= FTDMAC020_CH_CSR_SRC_WIDTH_SHIFT;
683 val = readl(ch->base + PL080S_CH_CONTROL2);
684 bytes = val & PL080S_CONTROL_TRANSFER_SIZE_MASK;
686 val = readl(ch->reg_control);
687 val &= PL080_CONTROL_SWIDTH_MASK;
688 val >>= PL080_CONTROL_SWIDTH_SHIFT;
691 val = readl(ch->reg_control);
692 bytes = val & PL080_CONTROL_TRANSFER_SIZE_MASK;
694 val &= PL080_CONTROL_SWIDTH_MASK;
695 val >>= PL080_CONTROL_SWIDTH_SHIFT;
698 switch (val) {
713 u32 val;
717 val = llis_va[PL080_LLI_CCTL];
718 bytes = val & FTDMAC020_LLI_TRANSFER_SIZE_MASK;
720 val = llis_va[PL080_LLI_CCTL];
721 val &= FTDMAC020_LLI_SRC_WIDTH_MSK;
722 val >>= FTDMAC020_LLI_SRC_WIDTH_SHIFT;
724 val = llis_va[PL080S_LLI_CCTL2];
725 bytes = val & PL080S_CONTROL_TRANSFER_SIZE_MASK;
727 val = llis_va[PL080_LLI_CCTL];
728 val &= PL080_CONTROL_SWIDTH_MASK;
729 val >>= PL080_CONTROL_SWIDTH_SHIFT;
732 val = llis_va[PL080_LLI_CCTL];
733 bytes = val & PL080_CONTROL_TRANSFER_SIZE_MASK;
735 val &= PL080_CONTROL_SWIDTH_MASK;
736 val >>= PL080_CONTROL_SWIDTH_SHIFT;
739 switch (val) {
971 u32 val;
975 val = (cctl & FTDMAC020_LLI_SRC_WIDTH_MSK) >>
978 val = (cctl & FTDMAC020_LLI_DST_WIDTH_MSK) >>
982 val = (cctl & PL080_CONTROL_SWIDTH_MASK) >>
985 val = (cctl & PL080_CONTROL_DWIDTH_MASK) >>
989 switch (val) {
2578 u32 val;
2607 ret = of_property_read_u32(np, "memcpy-burst-size", &val);
2610 val = 1;
2612 switch (val) {
2642 ret = of_property_read_u32(np, "memcpy-bus-width", &val);
2645 val = 8;
2647 switch (val) {
2737 u32 val;
2739 val = readl(pl08x->base + FTDMAC020_REVISION);
2741 (val >> 16) & 0xff, (val >> 8) & 0xff, val & 0xff);
2742 val = readl(pl08x->base + FTDMAC020_FEATURE);
2745 (val >> 12) & 0x0f,
2746 (val & BIT(10)) ? "no" : "has",
2747 (val & BIT(9)) ? "AHB0 and AHB1" : "AHB0",
2748 (val & BIT(8)) ? "supports" : "does not support");
2751 if (!(val & BIT(8)))
2754 vd->channels = (val >> 12) & 0x0f;
2755 vd->dualmaster = !!(val & BIT(9));
2908 u32 val;
2910 val = readl(ch->reg_config);
2911 if (val & (PL080N_CONFIG_ITPROT | PL080N_CONFIG_SECPROT)) {