Lines Matching defs:base
140 * @base: memory base address for this physical channel
158 void __iomem *base;
267 * @base: virtual memory base (remapped) for the PL08x
282 void __iomem *base;
424 phychan->base + FTDMAC020_CH_SIZE);
516 phychan->base + PL080S_CH_CONTROL2);
547 while (readl(pl08x->base + PL080_EN_CHAN) & BIT(phychan->id))
656 pl08x->base + PL080_ERR_CLEAR);
657 writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR);
667 writel(BIT(ch->id), pl08x->base + PL080_ERR_CLEAR);
668 writel(BIT(ch->id), pl08x->base + PL080_TC_CLEAR);
677 bytes = readl(ch->base + FTDMAC020_CH_SIZE);
683 val = readl(ch->base + PL080S_CH_CONTROL2);
2286 writel(PL080_CONFIG_ENABLE, pl08x->base + FTDMAC020_CSR);
2289 writel(PL080_CONFIG_ENABLE, pl08x->base + PL080_CONFIG);
2298 err = readl(pl08x->base + PL080_ERR_STATUS);
2302 writel(err, pl08x->base + PL080_ERR_CLEAR);
2304 tc = readl(pl08x->base + PL080_TC_STATUS);
2306 writel(tc, pl08x->base + PL080_TC_CLEAR);
2730 pl08x->base = ioremap(adev->res.start, resource_size(&adev->res));
2731 if (!pl08x->base) {
2739 val = readl(pl08x->base + FTDMAC020_REVISION);
2742 val = readl(pl08x->base + FTDMAC020_FEATURE);
2855 writel(0x0000FFFF, pl08x->base + PL080_ERR_CLEAR);
2857 writel(0x000000FF, pl08x->base + PL080_ERR_CLEAR);
2858 writel(0x000000FF, pl08x->base + PL080_TC_CLEAR);
2880 ch->base = pl08x->base + PL080_Cx_BASE(i);
2883 ch->reg_busy = ch->base + FTDMAC020_CH_BUSY;
2884 ch->reg_config = ch->base + FTDMAC020_CH_CFG;
2885 ch->reg_control = ch->base + FTDMAC020_CH_CSR;
2886 ch->reg_src = ch->base + FTDMAC020_CH_SRC_ADDR;
2887 ch->reg_dst = ch->base + FTDMAC020_CH_DST_ADDR;
2888 ch->reg_lli = ch->base + FTDMAC020_CH_LLP;
2891 ch->reg_config = ch->base + vd->config_offset;
2892 ch->reg_control = ch->base + PL080_CH_CONTROL;
2893 ch->reg_src = ch->base + PL080_CH_SRC_ADDR;
2894 ch->reg_dst = ch->base + PL080_CH_DST_ADDR;
2895 ch->reg_lli = ch->base + PL080_CH_LLI;
2984 iounmap(pl08x->base);