Lines Matching refs:crc
104 struct stm32_crc *crc;
107 crc = list_first_entry_or_null(&crc_list.dev_list, struct stm32_crc, list);
108 if (crc)
109 list_move_tail(&crc->list, &crc_list.dev_list);
112 return crc;
119 struct stm32_crc *crc;
122 crc = stm32_crc_get_next_crc();
123 if (!crc)
126 pm_runtime_get_sync(crc->dev);
128 spin_lock_irqsave(&crc->lock, flags);
131 writel_relaxed(bitrev32(mctx->key), crc->regs + CRC_INIT);
132 writel_relaxed(bitrev32(mctx->poly), crc->regs + CRC_POL);
134 crc->regs + CRC_CR);
137 ctx->partial = readl_relaxed(crc->regs + CRC_DR);
139 spin_unlock_irqrestore(&crc->lock, flags);
141 pm_runtime_mark_last_busy(crc->dev);
142 pm_runtime_put_autosuspend(crc->dev);
152 struct stm32_crc *crc;
154 crc = stm32_crc_get_next_crc();
155 if (!crc)
158 pm_runtime_get_sync(crc->dev);
160 if (!spin_trylock(&crc->lock)) {
176 writel_relaxed(bitrev32(ctx->partial), crc->regs + CRC_INIT);
177 writel_relaxed(bitrev32(mctx->poly), crc->regs + CRC_POL);
179 crc->regs + CRC_CR);
184 crc->regs + CRC_CR);
186 writeb_relaxed(*d8++, crc->regs + CRC_DR);
191 crc->regs + CRC_CR);
195 writel_relaxed(*((u32 *)d8), crc->regs + CRC_DR);
200 crc->regs + CRC_CR);
202 writeb_relaxed(*d8++, crc->regs + CRC_DR);
206 ctx->partial = readl_relaxed(crc->regs + CRC_DR);
208 spin_unlock(&crc->lock);
211 pm_runtime_mark_last_busy(crc->dev);
212 pm_runtime_put_autosuspend(crc->dev);
319 struct stm32_crc *crc;
322 crc = devm_kzalloc(dev, sizeof(*crc), GFP_KERNEL);
323 if (!crc)
326 crc->dev = dev;
328 crc->regs = devm_platform_ioremap_resource(pdev, 0);
329 if (IS_ERR(crc->regs)) {
331 return PTR_ERR(crc->regs);
334 crc->clk = devm_clk_get(dev, NULL);
335 if (IS_ERR(crc->clk)) {
337 return PTR_ERR(crc->clk);
340 ret = clk_prepare_enable(crc->clk);
342 dev_err(crc->dev, "Failed to enable clock\n");
354 spin_lock_init(&crc->lock);
356 platform_set_drvdata(pdev, crc);
359 list_add(&crc->list, &crc_list.dev_list);
368 clk_disable_unprepare(crc->clk);
384 struct stm32_crc *crc = platform_get_drvdata(pdev);
385 int ret = pm_runtime_get_sync(crc->dev);
388 pm_runtime_put_noidle(crc->dev);
393 list_del(&crc->list);
401 pm_runtime_disable(crc->dev);
402 pm_runtime_put_noidle(crc->dev);
404 clk_disable_unprepare(crc->clk);
411 struct stm32_crc *crc = dev_get_drvdata(dev);
418 clk_unprepare(crc->clk);
425 struct stm32_crc *crc = dev_get_drvdata(dev);
428 ret = clk_prepare(crc->clk);
430 dev_err(crc->dev, "Failed to prepare clock\n");
439 struct stm32_crc *crc = dev_get_drvdata(dev);
441 clk_disable(crc->clk);
448 struct stm32_crc *crc = dev_get_drvdata(dev);
451 ret = clk_enable(crc->clk);
453 dev_err(crc->dev, "Failed to enable clock\n");
468 { .compatible = "st,stm32f7-crc", },