Lines Matching refs:base
233 * @aes_offset: AES register offset from SSS module's base.
234 * @hash_offset: HASH register offset from SSS module's base.
504 req->base.complete(&req->base, err);
1359 if (req->base.complete)
1360 req->base.complete(&req->base, err);
1491 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1556 struct s5p_hash_ctx *tctx = crypto_tfm_ctx(req->base.tfm);
1743 .halg.base = {
1768 .halg.base = {
1793 .halg.base = {
1999 dev->ctx = crypto_tfm_ctx(dev->req->base.tfm);
2012 err = crypto_enqueue_request(&dev->queue, &req->base);
2101 .base.cra_name = "ecb(aes)",
2102 .base.cra_driver_name = "ecb-aes-s5p",
2103 .base.cra_priority = 100,
2104 .base.cra_flags = CRYPTO_ALG_ASYNC |
2106 .base.cra_blocksize = AES_BLOCK_SIZE,
2107 .base.cra_ctxsize = sizeof(struct s5p_aes_ctx),
2108 .base.cra_alignmask = 0x0f,
2109 .base.cra_module = THIS_MODULE,
2119 .base.cra_name = "cbc(aes)",
2120 .base.cra_driver_name = "cbc-aes-s5p",
2121 .base.cra_priority = 100,
2122 .base.cra_flags = CRYPTO_ALG_ASYNC |
2124 .base.cra_blocksize = AES_BLOCK_SIZE,
2125 .base.cra_ctxsize = sizeof(struct s5p_aes_ctx),
2126 .base.cra_alignmask = 0x0f,
2127 .base.cra_module = THIS_MODULE,
2138 .base.cra_name = "ctr(aes)",
2139 .base.cra_driver_name = "ctr-aes-s5p",
2140 .base.cra_priority = 100,
2141 .base.cra_flags = CRYPTO_ALG_ASYNC |
2143 .base.cra_blocksize = 1,
2144 .base.cra_ctxsize = sizeof(struct s5p_aes_ctx),
2145 .base.cra_alignmask = 0x0f,
2146 .base.cra_module = THIS_MODULE,
2284 alg->halg.base.cra_driver_name, err);
2303 dev_err(dev, "can't register '%s': %d\n", algs[i].base.cra_name,