Lines Matching defs:qce
18 static inline u32 qce_read(struct qce_device *qce, u32 offset)
20 return readl(qce->base + offset);
23 static inline void qce_write(struct qce_device *qce, u32 offset, u32 val)
25 writel(val, qce->base + offset);
28 static inline void qce_write_array(struct qce_device *qce, u32 offset,
34 qce_write(qce, offset + i * sizeof(u32), val[i]);
38 qce_clear_array(struct qce_device *qce, u32 offset, unsigned int len)
43 qce_write(qce, offset + i * sizeof(u32), 0);
46 static u32 qce_config_reg(struct qce_device *qce, int little)
48 u32 beats = (qce->burst_size >> 3) - 1;
49 u32 pipe_pair = qce->pipe_pair_id;
78 static void qce_setup_config(struct qce_device *qce)
83 config = qce_config_reg(qce, 0);
86 qce_write(qce, REG_STATUS, 0);
87 qce_write(qce, REG_CONFIG, config);
90 static inline void qce_crypto_go(struct qce_device *qce)
92 qce_write(qce, REG_GOPROC, BIT(GO_SHIFT) | BIT(RESULTS_DUMP_SHIFT));
149 struct qce_device *qce = tmpl->qce;
161 qce_setup_config(qce);
164 qce_write(qce, REG_AUTH_SEG_CFG, 0);
165 qce_write(qce, REG_ENCR_SEG_CFG, 0);
166 qce_write(qce, REG_ENCR_SEG_SIZE, 0);
167 qce_clear_array(qce, REG_AUTH_IV0, 16);
168 qce_clear_array(qce, REG_AUTH_KEY0, 16);
169 qce_clear_array(qce, REG_AUTH_BYTECNT0, 4);
178 qce_write_array(qce, REG_AUTH_KEY0, (u32 *)mackey,
191 qce_write_array(qce, REG_AUTH_IV0, (u32 *)auth, iv_words);
194 qce_clear_array(qce, REG_AUTH_BYTECNT0, 4);
196 qce_write_array(qce, REG_AUTH_BYTECNT0,
212 qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);
213 qce_write(qce, REG_AUTH_SEG_SIZE, req->nbytes);
214 qce_write(qce, REG_AUTH_SEG_START, 0);
215 qce_write(qce, REG_ENCR_SEG_CFG, 0);
216 qce_write(qce, REG_SEG_SIZE, req->nbytes);
219 config = qce_config_reg(qce, 1);
220 qce_write(qce, REG_CONFIG, config);
222 qce_crypto_go(qce);
292 static void qce_xtskey(struct qce_device *qce, const u8 *enckey,
301 qce_write_array(qce, REG_ENCR_XTS_KEY0, xtskey, xtsklen);
305 qce_write(qce, REG_ENCR_XTS_DU_SIZE, xtsdusize);
315 struct qce_device *qce = tmpl->qce;
324 qce_setup_config(qce);
334 qce_write(qce, REG_AUTH_SEG_CFG, auth_cfg);
346 qce_xtskey(qce, ctx->enc_key, ctx->enc_keylen,
353 qce_write_array(qce, REG_ENCR_KEY0, (u32 *)enckey, enckey_words);
361 qce_write_array(qce, REG_CNTR0_IV0, (u32 *)enciv, enciv_words);
367 qce_write(qce, REG_ENCR_SEG_CFG, encr_cfg);
368 qce_write(qce, REG_ENCR_SEG_SIZE, rctx->cryptlen);
369 qce_write(qce, REG_ENCR_SEG_START, offset & 0xffff);
372 qce_write(qce, REG_CNTR_MASK, ~0);
373 qce_write(qce, REG_CNTR_MASK0, ~0);
374 qce_write(qce, REG_CNTR_MASK1, ~0);
375 qce_write(qce, REG_CNTR_MASK2, ~0);
378 qce_write(qce, REG_SEG_SIZE, totallen);
381 config = qce_config_reg(qce, 1);
382 qce_write(qce, REG_CONFIG, config);
384 qce_crypto_go(qce);
410 int qce_check_status(struct qce_device *qce, u32 *status)
414 *status = qce_read(qce, REG_STATUS);
428 void qce_get_version(struct qce_device *qce, u32 *major, u32 *minor, u32 *step)
432 val = qce_read(qce, REG_VERSION);