Lines Matching defs:engine
81 struct spacc_engine *engine;
96 struct spacc_engine *engine;
139 struct spacc_engine *engine;
147 struct spacc_engine *engine;
187 static inline int spacc_fifo_cmd_full(struct spacc_engine *engine)
189 u32 fifo_stat = readl(engine->regs + SPA_FIFO_STAT_REG_OFFSET);
205 return is_cipher_ctx ? ctx->engine->cipher_ctx_base +
206 (indx * ctx->engine->cipher_pg_sz) :
207 ctx->engine->hash_key_base + (indx * ctx->engine->hash_pg_sz);
241 unsigned indx = ctx->engine->next_ctx++;
247 ctx->engine->next_ctx &= ctx->engine->fifo_sz - 1;
252 ctx->engine->regs + SPA_KEY_SZ_REG_OFFSET);
257 ctx->engine->regs + SPA_KEY_SZ_REG_OFFSET);
274 static struct spacc_ddt *spacc_sg_to_ddt(struct spacc_engine *engine,
288 dev_err(engine->dev, "Invalid numbers of SG.\n");
291 mapped_ents = dma_map_sg(engine->dev, payload, nents, dir);
296 ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, ddt_phys);
307 dma_unmap_sg(engine->dev, payload, nents, dir);
315 struct spacc_engine *engine = req->engine;
328 dev_err(engine->dev, "Invalid numbers of src SG.\n");
338 dev_err(engine->dev, "Invalid numbers of dst SG.\n");
345 src_ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, &req->src_addr);
349 dst_ddt = dma_pool_alloc(engine->req_pool, GFP_ATOMIC, &req->dst_addr);
357 src_ents = dma_map_sg(engine->dev, areq->src, src_nents,
362 dst_ents = dma_map_sg(engine->dev, areq->dst, dst_nents,
366 dma_unmap_sg(engine->dev, areq->src, src_nents,
371 src_ents = dma_map_sg(engine->dev, areq->src, src_nents,
404 dma_pool_free(engine->req_pool, dst_ddt, req->dst_addr);
406 dma_pool_free(engine->req_pool, src_ddt, req->src_addr);
419 struct spacc_engine *engine = aead_ctx->generic.engine;
424 dev_err(engine->dev, "Invalid numbers of src SG.\n");
429 dma_unmap_sg(engine->dev, areq->src, nents, DMA_TO_DEVICE);
432 dev_err(engine->dev, "Invalid numbers of dst SG.\n");
435 dma_unmap_sg(engine->dev, areq->dst, nents, DMA_FROM_DEVICE);
437 dma_unmap_sg(engine->dev, areq->src, nents, DMA_BIDIRECTIONAL);
439 dma_pool_free(engine->req_pool, req->src_ddt, req->src_addr);
440 dma_pool_free(engine->req_pool, req->dst_ddt, req->dst_addr);
450 dev_err(req->engine->dev, "Invalid numbers of SG.\n");
454 dma_unmap_sg(req->engine->dev, payload, nents, dir);
455 dma_pool_free(req->engine->req_pool, ddt, ddt_addr);
561 struct spacc_engine *engine = ctx->generic.engine;
570 writel(req->src_addr, engine->regs + SPA_SRC_PTR_REG_OFFSET);
571 writel(req->dst_addr, engine->regs + SPA_DST_PTR_REG_OFFSET);
572 writel(0, engine->regs + SPA_OFFSET_REG_OFFSET);
584 writel(proc_len, engine->regs + SPA_PROC_LEN_REG_OFFSET);
585 writel(assoc_len, engine->regs + SPA_AAD_LEN_REG_OFFSET);
586 writel(authsize, engine->regs + SPA_ICV_LEN_REG_OFFSET);
587 writel(0, engine->regs + SPA_ICV_OFFSET_REG_OFFSET);
588 writel(0, engine->regs + SPA_AUX_INFO_REG_OFFSET);
597 mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT);
599 writel(ctrl, engine->regs + SPA_CTRL_REG_OFFSET);
606 static void spacc_push(struct spacc_engine *engine)
610 while (!list_empty(&engine->pending) &&
611 engine->in_flight + 1 <= engine->fifo_sz) {
613 ++engine->in_flight;
614 req = list_first_entry(&engine->pending, struct spacc_req,
616 list_move_tail(&req->list, &engine->in_progress);
623 * Setup an AEAD request for processing. This will configure the engine, load
631 struct spacc_engine *engine = to_spacc_aead(alg)->engine;
639 dev_req->engine = engine;
650 spin_lock_irqsave(&engine->hw_lock, flags);
651 if (unlikely(spacc_fifo_cmd_full(engine)) ||
652 engine->in_flight + 1 > engine->fifo_sz) {
655 spin_unlock_irqrestore(&engine->hw_lock, flags);
658 list_add_tail(&dev_req->list, &engine->pending);
660 list_add_tail(&dev_req->list, &engine->pending);
661 spacc_push(engine);
663 spin_unlock_irqrestore(&engine->hw_lock, flags);
698 struct spacc_engine *engine = spacc_alg->engine;
701 ctx->generic.engine = engine;
784 * IPSec engine only supports 128 and 256 bit AES keys. If we get a
871 struct spacc_engine *engine = ctx->generic.engine;
878 writel(req->src_addr, engine->regs + SPA_SRC_PTR_REG_OFFSET);
879 writel(req->dst_addr, engine->regs + SPA_DST_PTR_REG_OFFSET);
880 writel(0, engine->regs + SPA_OFFSET_REG_OFFSET);
882 writel(ablk_req->cryptlen, engine->regs + SPA_PROC_LEN_REG_OFFSET);
883 writel(0, engine->regs + SPA_ICV_OFFSET_REG_OFFSET);
884 writel(0, engine->regs + SPA_AUX_INFO_REG_OFFSET);
885 writel(0, engine->regs + SPA_AAD_LEN_REG_OFFSET);
891 mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT);
893 writel(ctrl, engine->regs + SPA_CTRL_REG_OFFSET);
928 struct spacc_engine *engine = to_spacc_skcipher(alg)->engine;
935 dev_req->engine = engine;
943 * Create the DDT's for the engine. If we share the same source and
947 dev_req->src_ddt = spacc_sg_to_ddt(engine, req->src,
952 dev_req->dst_ddt = spacc_sg_to_ddt(engine, req->dst,
957 dev_req->dst_ddt = spacc_sg_to_ddt(engine, req->dst,
967 spin_lock_irqsave(&engine->hw_lock, flags);
969 * Check if the engine will accept the operation now. If it won't then
973 if (unlikely(spacc_fifo_cmd_full(engine)) ||
974 engine->in_flight + 1 > engine->fifo_sz) {
977 spin_unlock_irqrestore(&engine->hw_lock, flags);
980 list_add_tail(&dev_req->list, &engine->pending);
982 list_add_tail(&dev_req->list, &engine->pending);
983 spacc_push(engine);
985 spin_unlock_irqrestore(&engine->hw_lock, flags);
1006 struct spacc_engine *engine = spacc_alg->engine;
1009 ctx->generic.engine = engine;
1014 dev_warn(engine->dev, "failed to allocate fallback for %s\n",
1057 static inline int spacc_fifo_stat_empty(struct spacc_engine *engine)
1059 return readl(engine->regs + SPA_FIFO_STAT_REG_OFFSET) &
1063 static void spacc_process_done(struct spacc_engine *engine)
1068 spin_lock_irqsave(&engine->hw_lock, flags);
1070 while (!spacc_fifo_stat_empty(engine)) {
1071 req = list_first_entry(&engine->in_progress, struct spacc_req,
1073 list_move_tail(&req->list, &engine->completed);
1074 --engine->in_flight;
1077 writel(~0, engine->regs + SPA_STAT_POP_REG_OFFSET);
1078 req->result = (readl(engine->regs + SPA_STATUS_REG_OFFSET) &
1092 dev_warn(engine->dev,
1098 dev_warn(engine->dev,
1106 tasklet_schedule(&engine->complete);
1108 spin_unlock_irqrestore(&engine->hw_lock, flags);
1113 struct spacc_engine *engine = (struct spacc_engine *)dev;
1114 u32 spacc_irq_stat = readl(engine->regs + SPA_IRQ_STAT_REG_OFFSET);
1116 writel(spacc_irq_stat, engine->regs + SPA_IRQ_STAT_REG_OFFSET);
1117 spacc_process_done(engine);
1124 struct spacc_engine *engine = from_timer(engine, t, packet_timeout);
1126 spacc_process_done(engine);
1141 struct spacc_engine *engine = (struct spacc_engine *)data;
1146 spin_lock_irqsave(&engine->hw_lock, flags);
1148 list_splice_init(&engine->completed, &completed);
1149 spacc_push(engine);
1150 if (engine->in_flight)
1151 mod_timer(&engine->packet_timeout, jiffies + PACKET_TIMEOUT);
1153 spin_unlock_irqrestore(&engine->hw_lock, flags);
1164 struct spacc_engine *engine = dev_get_drvdata(dev);
1171 clk_disable(engine->clk);
1178 struct spacc_engine *engine = dev_get_drvdata(dev);
1180 return clk_enable(engine->clk);
1198 struct spacc_engine *engine = spacc_dev_to_engine(dev);
1200 return snprintf(buf, PAGE_SIZE, "%u\n", engine->stat_irq_thresh);
1207 struct spacc_engine *engine = spacc_dev_to_engine(dev);
1213 thresh = clamp(thresh, 1UL, engine->fifo_sz - 1);
1215 engine->stat_irq_thresh = thresh;
1216 writel(engine->stat_irq_thresh << SPA_IRQ_CTRL_STAT_CNT_OFFSET,
1217 engine->regs + SPA_IRQ_CTRL_REG_OFFSET);
1614 struct spacc_engine *engine = devm_kzalloc(&pdev->dev, sizeof(*engine),
1616 if (!engine)
1620 engine->max_ctxs = SPACC_CRYPTO_IPSEC_MAX_CTXS;
1621 engine->cipher_pg_sz = SPACC_CRYPTO_IPSEC_CIPHER_PG_SZ;
1622 engine->hash_pg_sz = SPACC_CRYPTO_IPSEC_HASH_PG_SZ;
1623 engine->fifo_sz = SPACC_CRYPTO_IPSEC_FIFO_SZ;
1624 engine->algs = ipsec_engine_algs;
1625 engine->num_algs = ARRAY_SIZE(ipsec_engine_algs);
1626 engine->aeads = ipsec_engine_aeads;
1627 engine->num_aeads = ARRAY_SIZE(ipsec_engine_aeads);
1629 engine->max_ctxs = SPACC_CRYPTO_L2_MAX_CTXS;
1630 engine->cipher_pg_sz = SPACC_CRYPTO_L2_CIPHER_PG_SZ;
1631 engine->hash_pg_sz = SPACC_CRYPTO_L2_HASH_PG_SZ;
1632 engine->fifo_sz = SPACC_CRYPTO_L2_FIFO_SZ;
1633 engine->algs = l2_engine_algs;
1634 engine->num_algs = ARRAY_SIZE(l2_engine_algs);
1639 engine->name = dev_name(&pdev->dev);
1641 engine->regs = devm_platform_ioremap_resource(pdev, 0);
1642 if (IS_ERR(engine->regs))
1643 return PTR_ERR(engine->regs);
1647 dev_err(&pdev->dev, "no memory/irq resource for engine\n");
1651 tasklet_init(&engine->complete, spacc_spacc_complete,
1652 (unsigned long)engine);
1655 &engine->complete);
1660 engine->name, engine)) {
1661 dev_err(engine->dev, "failed to request IRQ\n");
1665 engine->dev = &pdev->dev;
1666 engine->cipher_ctx_base = engine->regs + SPA_CIPH_KEY_BASE_REG_OFFSET;
1667 engine->hash_key_base = engine->regs + SPA_HASH_KEY_BASE_REG_OFFSET;
1669 engine->req_pool = dmam_pool_create(engine->name, engine->dev,
1671 if (!engine->req_pool)
1674 spin_lock_init(&engine->hw_lock);
1676 engine->clk = clk_get(&pdev->dev, "ref");
1677 if (IS_ERR(engine->clk)) {
1679 return PTR_ERR(engine->clk);
1682 if (clk_prepare_enable(engine->clk)) {
1693 engine->stat_irq_thresh = (engine->fifo_sz / 2);
1704 writel(engine->stat_irq_thresh << SPA_IRQ_CTRL_STAT_CNT_OFFSET,
1705 engine->regs + SPA_IRQ_CTRL_REG_OFFSET);
1707 engine->regs + SPA_IRQ_EN_REG_OFFSET);
1709 timer_setup(&engine->packet_timeout, spacc_packet_timeout, 0);
1711 INIT_LIST_HEAD(&engine->pending);
1712 INIT_LIST_HEAD(&engine->completed);
1713 INIT_LIST_HEAD(&engine->in_progress);
1714 engine->in_flight = 0;
1716 platform_set_drvdata(pdev, engine);
1719 INIT_LIST_HEAD(&engine->registered_algs);
1720 for (i = 0; i < engine->num_algs; ++i) {
1721 engine->algs[i].engine = engine;
1722 err = crypto_register_skcipher(&engine->algs[i].alg);
1724 list_add_tail(&engine->algs[i].entry,
1725 &engine->registered_algs);
1729 dev_err(engine->dev, "failed to register alg \"%s\"\n",
1730 engine->algs[i].alg.base.cra_name);
1732 dev_dbg(engine->dev, "registered alg \"%s\"\n",
1733 engine->algs[i].alg.base.cra_name);
1736 INIT_LIST_HEAD(&engine->registered_aeads);
1737 for (i = 0; i < engine->num_aeads; ++i) {
1738 engine->aeads[i].engine = engine;
1739 err = crypto_register_aead(&engine->aeads[i].alg);
1741 list_add_tail(&engine->aeads[i].entry,
1742 &engine->registered_aeads);
1746 dev_err(engine->dev, "failed to register alg \"%s\"\n",
1747 engine->aeads[i].alg.base.cra_name);
1749 dev_dbg(engine->dev, "registered alg \"%s\"\n",
1750 engine->aeads[i].alg.base.cra_name);
1756 del_timer_sync(&engine->packet_timeout);
1759 clk_disable_unprepare(engine->clk);
1761 clk_put(engine->clk);
1770 struct spacc_engine *engine = platform_get_drvdata(pdev);
1772 del_timer_sync(&engine->packet_timeout);
1775 list_for_each_entry_safe(aead, an, &engine->registered_aeads, entry) {
1780 list_for_each_entry_safe(alg, next, &engine->registered_algs, entry) {
1785 clk_disable_unprepare(engine->clk);
1786 clk_put(engine->clk);