Lines Matching refs:base
123 writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DFE_THR_CTRL);
124 writel(MTK_DFSE_THR_CTRL_EN | mask, cryp->base + DSE_THR_CTRL);
140 cryp->base + DFE_CFG);
144 cryp->base + DSE_CFG);
148 cryp->base + PE_IN_DBUF_THRESH);
152 cryp->base + PE_IN_TBUF_THRESH);
156 cryp->base + PE_OUT_DBUF_THRESH);
158 writel(0, cryp->base + PE_OUT_TBUF_THRESH);
159 writel(0, cryp->base + PE_OUT_BUF_CTRL);
168 val = readl(cryp->base + DFE_THR_STAT);
170 val = readl(cryp->base + DSE_THR_STAT);
177 writel(0, cryp->base + DFE_THR_CTRL);
178 writel(0, cryp->base + DSE_THR_CTRL);
189 writel(MTK_DFSE_THR_CTRL_RESET, cryp->base + DFE_THR_CTRL);
190 writel(0, cryp->base + DFE_PRIO_0);
191 writel(0, cryp->base + DFE_PRIO_1);
192 writel(0, cryp->base + DFE_PRIO_2);
193 writel(0, cryp->base + DFE_PRIO_3);
195 writel(MTK_DFSE_THR_CTRL_RESET, cryp->base + DSE_THR_CTRL);
196 writel(0, cryp->base + DSE_PRIO_0);
197 writel(0, cryp->base + DSE_PRIO_1);
198 writel(0, cryp->base + DSE_PRIO_2);
199 writel(0, cryp->base + DSE_PRIO_3);
212 writel(0, cryp->base + CDR_CFG(i));
215 writel(MTK_CNT_RST, cryp->base + CDR_PREP_COUNT(i));
216 writel(MTK_CNT_RST, cryp->base + CDR_PROC_COUNT(i));
218 writel(0, cryp->base + CDR_PREP_PNTR(i));
219 writel(0, cryp->base + CDR_PROC_PNTR(i));
220 writel(0, cryp->base + CDR_DMA_CFG(i));
223 writel(0, cryp->base + CDR_BASE_ADDR_HI(i));
224 writel(cryp->ring[i]->cmd_dma, cryp->base + CDR_BASE_ADDR_LO(i));
226 writel(MTK_DESC_RING_SZ, cryp->base + CDR_RING_SIZE(i));
229 writel(MTK_CDR_STAT_CLR, cryp->base + CDR_STAT(i));
238 cryp->base + CDR_DESC_SIZE(i));
242 cryp->base + CDR_CFG(i));
252 writel(0, cryp->base + RDR_CFG(i));
255 writel(MTK_CNT_RST, cryp->base + RDR_PREP_COUNT(i));
256 writel(MTK_CNT_RST, cryp->base + RDR_PROC_COUNT(i));
258 writel(0, cryp->base + RDR_PREP_PNTR(i));
259 writel(0, cryp->base + RDR_PROC_PNTR(i));
260 writel(0, cryp->base + RDR_DMA_CFG(i));
263 writel(0, cryp->base + RDR_BASE_ADDR_HI(i));
264 writel(cryp->ring[i]->res_dma, cryp->base + RDR_BASE_ADDR_LO(i));
266 writel(MTK_DESC_RING_SZ, cryp->base + RDR_RING_SIZE(i));
267 writel(MTK_RDR_STAT_CLR, cryp->base + RDR_STAT(i));
275 cryp->base + RDR_THRESH(i));
283 cryp->base + RDR_DESC_SIZE(i));
292 cryp->base + RDR_CFG(i));
301 cap.hia_ver = readl(cryp->base + HIA_VERSION);
302 cap.hia_opt = readl(cryp->base + HIA_OPTIONS);
303 cap.hw_opt = readl(cryp->base + EIP97_OPTIONS);
309 writel(0, cryp->base + EIP97_MST_CTRL);
312 val = readl(cryp->base + HIA_MST_CTRL);
315 writel(val, cryp->base + HIA_MST_CTRL);
334 cryp->base + PE_TOKEN_CTRL_STAT);
337 writel(MTK_AIC_G_CLR, cryp->base + AIC_G_ACK);
344 cryp->base + PE_INTERRUPT_CTRL_STAT);
354 val = readl(cryp->base + AIC_G_VERSION);
356 val = readl(cryp->base + AIC_VERSION(hw));
363 val = readl(cryp->base + AIC_G_OPTIONS);
365 val = readl(cryp->base + AIC_OPTIONS(hw));
384 writel(0, cryp->base + AIC_G_ENABLE_CTRL);
385 writel(0, cryp->base + AIC_G_POL_CTRL);
386 writel(0, cryp->base + AIC_G_TYPE_CTRL);
387 writel(0, cryp->base + AIC_G_ENABLE_SET);
389 writel(0, cryp->base + AIC_ENABLE_CTRL(hw));
390 writel(0, cryp->base + AIC_POL_CTRL(hw));
391 writel(0, cryp->base + AIC_TYPE_CTRL(hw));
392 writel(0, cryp->base + AIC_ENABLE_SET(hw));
485 cryp->base = devm_platform_ioremap_resource(pdev, 0);
486 if (IS_ERR(cryp->base))
487 return PTR_ERR(cryp->base);