Lines Matching defs:engine
39 struct mv_cesa_engine *engine = dreq->engine;
41 writel_relaxed(0, engine->regs + CESA_SA_CFG);
43 mv_cesa_set_int_mask(engine, CESA_SA_INT_ACC0_IDMA_DONE);
46 engine->regs + CESA_TDMA_CONTROL);
50 engine->regs + CESA_SA_CFG);
52 engine->regs + CESA_TDMA_NEXT_ADDR);
53 WARN_ON(readl(engine->regs + CESA_SA_CMD) &
55 writel(CESA_SA_CMD_EN_CESA_SA_ACCL0, engine->regs + CESA_SA_CMD);
80 struct mv_cesa_engine *engine)
86 tdma->dst = cpu_to_le32(tdma->dst_dma + engine->sram_dma);
89 tdma->src = cpu_to_le32(tdma->src_dma + engine->sram_dma);
92 mv_cesa_adjust_op(engine, tdma->op);
96 void mv_cesa_tdma_chain(struct mv_cesa_engine *engine,
99 if (engine->chain.first == NULL && engine->chain.last == NULL) {
100 engine->chain.first = dreq->chain.first;
101 engine->chain.last = dreq->chain.last;
105 last = engine->chain.last;
107 engine->chain.last = dreq->chain.last;
121 int mv_cesa_tdma_process(struct mv_cesa_engine *engine, u32 status)
128 tdma_cur = readl(engine->regs + CESA_TDMA_CUR);
130 for (tdma = engine->chain.first; tdma; tdma = next) {
131 spin_lock_bh(&engine->lock);
133 spin_unlock_bh(&engine->lock);
140 spin_lock_bh(&engine->lock);
143 * request in engine->req.
146 req = engine->req;
148 req = mv_cesa_dequeue_req_locked(engine,
152 engine->chain.first = tdma->next;
156 if (engine->chain.first == NULL)
157 engine->chain.last = NULL;
158 spin_unlock_bh(&engine->lock);
167 mv_cesa_engine_enqueue_complete_request(engine,
179 * Save the last request in error to engine->req, so that the core
183 spin_lock_bh(&engine->lock);
184 engine->req = req;
185 spin_unlock_bh(&engine->lock);