Lines Matching defs:engine
5 * driver supports the TDMA engine on platforms on which it is available.
38 mv_cesa_dequeue_req_locked(struct mv_cesa_engine *engine,
43 *backlog = crypto_get_backlog(&engine->queue);
44 req = crypto_dequeue_request(&engine->queue);
52 static void mv_cesa_rearm_engine(struct mv_cesa_engine *engine)
58 spin_lock_bh(&engine->lock);
59 if (!engine->req) {
60 req = mv_cesa_dequeue_req_locked(engine, &backlog);
61 engine->req = req;
63 spin_unlock_bh(&engine->lock);
75 static int mv_cesa_std_process(struct mv_cesa_engine *engine, u32 status)
81 req = engine->req;
87 mv_cesa_engine_enqueue_complete_request(engine, req);
95 static int mv_cesa_int_process(struct mv_cesa_engine *engine, u32 status)
97 if (engine->chain.first && engine->chain.last)
98 return mv_cesa_tdma_process(engine, status);
100 return mv_cesa_std_process(engine, status);
115 struct mv_cesa_engine *engine = priv;
124 mask = mv_cesa_get_int_mask(engine);
125 status = readl(engine->regs + CESA_SA_INT_STATUS);
134 writel(~status, engine->regs + CESA_SA_FPGA_INT_STATUS);
135 writel(~status, engine->regs + CESA_SA_INT_STATUS);
138 res = mv_cesa_int_process(engine, status & mask);
141 spin_lock_bh(&engine->lock);
142 req = engine->req;
144 engine->req = NULL;
145 spin_unlock_bh(&engine->lock);
153 mv_cesa_rearm_engine(engine);
157 req = mv_cesa_engine_dequeue_complete_request(engine);
173 struct mv_cesa_engine *engine = creq->engine;
175 spin_lock_bh(&engine->lock);
176 ret = crypto_enqueue_request(&engine->queue, req);
179 mv_cesa_tdma_chain(engine, creq);
180 spin_unlock_bh(&engine->lock);
185 mv_cesa_rearm_engine(engine);
315 mv_cesa_conf_mbus_windows(struct mv_cesa_engine *engine,
318 void __iomem *iobase = engine->regs;
377 struct mv_cesa_engine *engine = &cesa->engines[idx];
381 engine->pool = of_gen_pool_get(cesa->dev->of_node,
383 if (engine->pool) {
384 engine->sram = gen_pool_dma_alloc(engine->pool,
386 &engine->sram_dma);
387 if (engine->sram)
390 engine->pool = NULL;
406 engine->sram = devm_ioremap_resource(cesa->dev, res);
407 if (IS_ERR(engine->sram))
408 return PTR_ERR(engine->sram);
410 engine->sram_dma = dma_map_resource(cesa->dev, res->start,
413 if (dma_mapping_error(cesa->dev, engine->sram_dma))
422 struct mv_cesa_engine *engine = &cesa->engines[idx];
424 if (engine->pool)
425 gen_pool_free(engine->pool, (unsigned long)engine->sram,
428 dma_unmap_resource(cesa->dev, engine->sram_dma,
490 struct mv_cesa_engine *engine = &cesa->engines[i];
493 engine->id = i;
494 spin_lock_init(&engine->lock);
506 engine->irq = irq;
513 engine->clk = devm_clk_get(dev, res_name);
514 if (IS_ERR(engine->clk)) {
515 engine->clk = devm_clk_get(dev, NULL);
516 if (IS_ERR(engine->clk))
517 engine->clk = NULL;
521 engine->zclk = devm_clk_get(dev, res_name);
522 if (IS_ERR(engine->zclk))
523 engine->zclk = NULL;
525 ret = clk_prepare_enable(engine->clk);
529 ret = clk_prepare_enable(engine->zclk);
533 engine->regs = cesa->regs + CESA_ENGINE_OFF(i);
536 mv_cesa_conf_mbus_windows(engine, dram);
538 writel(0, engine->regs + CESA_SA_INT_STATUS);
540 engine->regs + CESA_SA_CFG);
541 writel(engine->sram_dma & CESA_SA_SRAM_MSK,
542 engine->regs + CESA_SA_DESC_P0);
547 engine);
552 cpu = cpumask_local_spread(engine->id, NUMA_NO_NODE);
555 crypto_init_queue(&engine->queue, CESA_CRYPTO_DEFAULT_MAX_QLEN);
556 atomic_set(&engine->load, 0);
557 INIT_LIST_HEAD(&engine->complete_queue);
621 MODULE_DESCRIPTION("Support for Marvell's cryptographic engine");