Lines Matching defs:version
413 if (priv->version == EIP197D_MRVL)
415 else if (priv->version == EIP197B_MRVL ||
416 priv->version == EIP197_DEVBRD)
426 if (minifw || priv->version != EIP197B_MRVL)
1405 u32 peid, version, mask, val, hiaopt, hwopt, peopt;
1415 * First try the EIP97 HIA version regs
1419 version = readl(priv->base + EIP97_HIA_AIC_BASE + EIP197_HIA_VERSION);
1422 if (EIP197_REG_LO16(version) == EIP197_HIA_VERSION_LE) {
1423 priv->hwconfig.hiaver = EIP197_VERSION_MASK(version);
1424 } else if (EIP197_REG_HI16(version) == EIP197_HIA_VERSION_BE) {
1427 priv->hwconfig.hiaver = EIP197_VERSION_SWAP(version);
1430 version = readl(priv->base + EIP197_HIA_AIC_BASE +
1432 if (EIP197_REG_LO16(version) == EIP197_HIA_VERSION_LE) {
1433 priv->hwconfig.hiaver = EIP197_VERSION_MASK(version);
1435 } else if (EIP197_REG_HI16(version) ==
1439 priv->hwconfig.hiaver = EIP197_VERSION_SWAP(version);
1450 * If the version was read byte-swapped, we need to flip the device
1465 version = readl(EIP197_GLOBAL(priv) + EIP197_VERSION);
1467 (EIP197_REG_LO16(version) != EIP197_VERSION_LE) &&
1468 (EIP197_REG_LO16(version) != EIP196_VERSION_LE)) ||
1470 (EIP197_REG_LO16(version) != EIP97_VERSION_LE)))) {
1476 version);
1480 priv->hwconfig.hwver = EIP197_VERSION_MASK(version);
1481 hwctg = version >> 28;
1482 peid = version & 255;
1485 version = readl(EIP197_PE(priv) + + EIP197_PE_VERSION(0));
1486 if (EIP197_REG_LO16(version) != EIP206_VERSION_LE) {
1490 priv->hwconfig.ppver = EIP197_VERSION_MASK(version);
1492 /* Detect EIP96 packet engine and version */
1493 version = readl(EIP197_PE(priv) + EIP197_PE_EIP96_VERSION(0));
1494 if (EIP197_REG_LO16(version) != EIP96_VERSION_LE) {
1498 priv->hwconfig.pever = EIP197_VERSION_MASK(version);
1526 /* Detect ICE EIP207 class. engine and version */
1527 version = readl(EIP197_PE(priv) +
1529 if (EIP197_REG_LO16(version) != EIP207_VERSION_LE) {
1534 priv->hwconfig.icever = EIP197_VERSION_MASK(version);
1538 /* Detect EIP96PP packet stream editor and version */
1539 version = readl(EIP197_PE(priv) + EIP197_PE_PSE_VERSION(0));
1540 if (EIP197_REG_LO16(version) != EIP96_VERSION_LE) {
1544 priv->hwconfig.psever = EIP197_VERSION_MASK(version);
1545 /* Detect OCE EIP207 class. engine and version */
1546 version = readl(EIP197_PE(priv) +
1548 if (EIP197_REG_LO16(version) != EIP207_VERSION_LE) {
1553 priv->hwconfig.ocever = EIP197_VERSION_MASK(version);
1575 version = readl(EIP197_HIA_AIC_R(priv) +
1577 if (EIP197_REG_LO16(version) != EIP201_VERSION_LE)
1603 if (IS_ENABLED(CONFIG_PCI) && priv->version == EIP197_DEVBRD) {
1754 priv->version = (enum safexcel_eip_version)of_device_get_match_data(dev);
1885 priv->version = (enum safexcel_eip_version)ent->driver_data;
1904 if (priv->version == EIP197_DEVBRD) {
1916 dev_dbg(dev, "Detected Xilinx PCIE IRQ block version %d, multiple MSI support enabled\n",