Lines Matching refs:qm
252 static int hisi_zip_set_user_domain_and_cache(struct hisi_qm *qm)
254 void __iomem *base = qm->io_base;
256 /* qm user domain */
263 /* qm cache */
282 if (qm->use_sva) {
302 static void hisi_zip_hw_error_enable(struct hisi_qm *qm)
306 if (qm->ver == QM_HW_V1) {
308 qm->io_base + HZIP_CORE_INT_MASK_REG);
309 dev_info(&qm->pdev->dev, "Does not support hw error handle\n");
314 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_SOURCE);
317 writel(0x1, qm->io_base + HZIP_CORE_INT_RAS_CE_ENB);
318 writel(0x0, qm->io_base + HZIP_CORE_INT_RAS_FE_ENB);
320 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
323 writel(0, qm->io_base + HZIP_CORE_INT_MASK_REG);
326 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
328 writel(val, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
331 static void hisi_zip_hw_error_disable(struct hisi_qm *qm)
336 writel(HZIP_CORE_INT_MASK_ALL, qm->io_base + HZIP_CORE_INT_MASK_REG);
339 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
341 writel(val, qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
348 return &hisi_zip->qm;
353 struct hisi_qm *qm = file_to_qm(file);
355 return readl(qm->io_base + QM_DFX_MB_CNT_VF);
360 struct hisi_qm *qm = file_to_qm(file);
364 if (val > qm->vfs_num)
369 qm->debug.curr_qm_qp_num = qm->qp_num;
371 vfq_num = (qm->ctrl_qp_num - qm->qp_num) / qm->vfs_num;
372 if (val == qm->vfs_num)
373 qm->debug.curr_qm_qp_num = qm->ctrl_qp_num -
374 qm->qp_num - (qm->vfs_num - 1) * vfq_num;
376 qm->debug.curr_qm_qp_num = vfq_num;
379 writel(val, qm->io_base + QM_DFX_MB_CNT_VF);
380 writel(val, qm->io_base + QM_DFX_DB_CNT_VF);
383 (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_Q_MASK);
384 writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
387 (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_Q_MASK);
388 writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
395 struct hisi_qm *qm = file_to_qm(file);
397 return readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &
403 struct hisi_qm *qm = file_to_qm(file);
409 tmp = (readl(qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE) &
411 writel(tmp, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
516 static int hisi_zip_core_debug_init(struct hisi_qm *qm)
518 struct device *dev = &qm->pdev->dev;
537 regset->base = qm->io_base + core_offsets[i];
539 tmp_d = debugfs_create_dir(buf, qm->debug.debug_root);
546 static void hisi_zip_dfx_debug_init(struct hisi_qm *qm)
548 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm);
554 tmp_dir = debugfs_create_dir("zip_dfx", qm->debug.debug_root);
563 static int hisi_zip_ctrl_debug_init(struct hisi_qm *qm)
565 struct hisi_zip *zip = container_of(qm, struct hisi_zip, qm);
574 qm->debug.debug_root,
579 return hisi_zip_core_debug_init(qm);
582 static int hisi_zip_debugfs_init(struct hisi_qm *qm)
584 struct device *dev = &qm->pdev->dev;
590 qm->debug.sqe_mask_offset = HZIP_SQE_MASK_OFFSET;
591 qm->debug.sqe_mask_len = HZIP_SQE_MASK_LEN;
592 qm->debug.debug_root = dev_d;
593 ret = hisi_qm_debug_init(qm);
597 if (qm->fun_type == QM_HW_PF) {
598 ret = hisi_zip_ctrl_debug_init(qm);
603 hisi_zip_dfx_debug_init(qm);
613 static void hisi_zip_debug_regs_clear(struct hisi_qm *qm)
618 writel(0x0, qm->io_base + QM_DFX_MB_CNT_VF);
619 writel(0x0, qm->io_base + QM_DFX_DB_CNT_VF);
622 writel(HZIP_RD_CNT_CLR_CE_EN, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
625 readl(qm->io_base + core_offsets[i] +
629 writel(0x0, qm->io_base + HZIP_SOFT_CTRL_CNT_CLR_CE);
631 hisi_qm_debug_regs_clear(qm);
634 static void hisi_zip_debugfs_exit(struct hisi_qm *qm)
636 debugfs_remove_recursive(qm->debug.debug_root);
638 if (qm->fun_type == QM_HW_PF) {
639 hisi_zip_debug_regs_clear(qm);
640 qm->debug.curr_qm_qp_num = 0;
644 static void hisi_zip_log_hw_error(struct hisi_qm *qm, u32 err_sts)
647 struct device *dev = &qm->pdev->dev;
656 err_val = readl(qm->io_base +
667 static u32 hisi_zip_get_hw_err_status(struct hisi_qm *qm)
669 return readl(qm->io_base + HZIP_CORE_INT_STATUS);
672 static void hisi_zip_clear_hw_err_status(struct hisi_qm *qm, u32 err_sts)
674 writel(err_sts, qm->io_base + HZIP_CORE_INT_SOURCE);
677 static void hisi_zip_open_axi_master_ooo(struct hisi_qm *qm)
681 val = readl(qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
684 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
687 qm->io_base + HZIP_SOFT_CTRL_ZIP_CONTROL);
690 static void hisi_zip_close_axi_master_ooo(struct hisi_qm *qm)
695 nfe_enb = readl(qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
697 qm->io_base + HZIP_CORE_INT_RAS_NFE_ENB);
701 qm->io_base + HZIP_CORE_INT_SET);
726 struct hisi_qm *qm = &hisi_zip->qm;
729 ctrl = devm_kzalloc(&qm->pdev->dev, sizeof(*ctrl), GFP_KERNEL);
736 if (qm->ver == QM_HW_V1)
737 qm->ctrl_qp_num = HZIP_QUEUE_NUM_V1;
739 qm->ctrl_qp_num = HZIP_QUEUE_NUM_V2;
741 qm->err_ini = &hisi_zip_err_ini;
743 hisi_zip_set_user_domain_and_cache(qm);
744 hisi_qm_dev_err_init(qm);
745 hisi_zip_debug_regs_clear(qm);
750 static int hisi_zip_qm_init(struct hisi_qm *qm, struct pci_dev *pdev)
752 qm->pdev = pdev;
753 qm->ver = pdev->revision;
754 qm->algs = "zlib\ngzip";
755 qm->sqe_size = HZIP_SQE_SIZE;
756 qm->dev_name = hisi_zip_name;
758 qm->fun_type = (pdev->device == PCI_DEVICE_ID_ZIP_PF) ?
760 if (qm->fun_type == QM_HW_PF) {
761 qm->qp_base = HZIP_PF_DEF_Q_BASE;
762 qm->qp_num = pf_q_num;
763 qm->debug.curr_qm_qp_num = pf_q_num;
764 qm->qm_list = &zip_devices;
765 } else if (qm->fun_type == QM_HW_VF && qm->ver == QM_HW_V1) {
767 * have no way to get qm configure in VM in v1 hardware,
773 qm->qp_base = HZIP_PF_DEF_Q_NUM;
774 qm->qp_num = HZIP_QUEUE_NUM_V1 - HZIP_PF_DEF_Q_NUM;
777 return hisi_qm_init(qm);
782 struct hisi_qm *qm = &hisi_zip->qm;
785 if (qm->fun_type == QM_HW_PF) {
797 struct hisi_qm *qm;
804 qm = &hisi_zip->qm;
806 ret = hisi_zip_qm_init(qm, pdev);
818 ret = hisi_qm_start(qm);
822 ret = hisi_zip_debugfs_init(qm);
826 ret = hisi_qm_alg_register(qm, &zip_devices);
832 if (qm->uacce) {
833 ret = uacce_register(qm->uacce);
840 if (qm->fun_type == QM_HW_PF && vfs_num > 0) {
849 hisi_qm_alg_unregister(qm, &zip_devices);
852 hisi_zip_debugfs_exit(qm);
853 hisi_qm_stop(qm, QM_NORMAL);
856 hisi_qm_dev_err_uninit(qm);
859 hisi_qm_uninit(qm);
866 struct hisi_qm *qm = pci_get_drvdata(pdev);
868 hisi_qm_wait_task_finish(qm, &zip_devices);
869 hisi_qm_alg_unregister(qm, &zip_devices);
871 if (qm->fun_type == QM_HW_PF && qm->vfs_num)
872 hisi_qm_sriov_disable(pdev, qm->is_frozen);
874 hisi_zip_debugfs_exit(qm);
875 hisi_qm_stop(qm, QM_NORMAL);
876 hisi_qm_dev_err_uninit(qm);
877 hisi_qm_uninit(qm);