Lines Matching defs:base
254 void __iomem *base = qm->io_base;
257 writel(AXUSER_BASE, base + QM_ARUSER_M_CFG_1);
258 writel(ARUSER_M_CFG_ENABLE, base + QM_ARUSER_M_CFG_ENABLE);
259 writel(AXUSER_BASE, base + QM_AWUSER_M_CFG_1);
260 writel(AWUSER_M_CFG_ENABLE, base + QM_AWUSER_M_CFG_ENABLE);
261 writel(WUSER_M_CFG_ENABLE, base + QM_WUSER_M_CFG_ENABLE);
264 writel(AXI_M_CFG, base + QM_AXI_M_CFG);
265 writel(AXI_M_CFG_ENABLE, base + QM_AXI_M_CFG_ENABLE);
268 writel(PEH_AXUSER_CFG, base + QM_PEH_AXUSER_CFG);
269 writel(PEH_AXUSER_CFG_ENABLE, base + QM_PEH_AXUSER_CFG_ENABLE);
272 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_0);
273 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_ARCA_CHE_1);
274 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_0);
275 writel(HZIP_CACHE_ALL_EN, base + HZIP_PORT_AWCA_CHE_1);
278 writel(AXUSER_BASE, base + HZIP_BD_RUSER_32_63);
279 writel(AXUSER_BASE, base + HZIP_SGL_RUSER_32_63);
280 writel(AXUSER_BASE, base + HZIP_BD_WUSER_32_63);
283 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_RUSER_32_63);
284 writel(AXUSER_BASE | AXUSER_SSV, base + HZIP_DATA_WUSER_32_63);
286 writel(AXUSER_BASE, base + HZIP_DATA_RUSER_32_63);
287 writel(AXUSER_BASE, base + HZIP_DATA_WUSER_32_63);
292 base + HZIP_CLOCK_GATE_CTRL);
297 FIELD_PREP(CQC_CACHE_WB_THRD, 1), base + QM_CACHE_CTL);
537 regset->base = qm->io_base + core_offsets[i];