Lines Matching refs:qm
18 #include "qm.h"
318 struct hisi_qm *qm;
324 int (*get_vft)(struct hisi_qm *qm, u32 *base, u32 *number);
325 void (*qm_db)(struct hisi_qm *qm, u16 qn,
327 u32 (*get_irq_num)(struct hisi_qm *qm);
328 int (*debug_init)(struct hisi_qm *qm);
329 void (*hw_error_init)(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe);
330 void (*hw_error_uninit)(struct hisi_qm *qm);
331 enum acc_err_result (*hw_error_handle)(struct hisi_qm *qm);
390 static bool qm_avail_state(struct hisi_qm *qm, enum qm_state new)
392 enum qm_state curr = atomic_read(&qm->status.flags);
412 dev_dbg(&qm->pdev->dev, "change qm state from %s to %s\n",
416 dev_warn(&qm->pdev->dev, "Can not change qm state from %s to %s\n",
422 static bool qm_qp_avail_state(struct hisi_qm *qm, struct hisi_qp *qp,
425 enum qm_state qm_curr = atomic_read(&qm->status.flags);
458 dev_dbg(&qm->pdev->dev, "change qp state from %s to %s in QM %s\n",
462 dev_warn(&qm->pdev->dev,
470 static int qm_wait_mb_ready(struct hisi_qm *qm)
474 return readl_relaxed_poll_timeout(qm->io_base + QM_MB_CMD_SEND_BASE,
480 static void qm_mb_write(struct hisi_qm *qm, const void *src)
482 void __iomem *fun_base = qm->io_base + QM_MB_CMD_SEND_BASE;
501 static int qm_mb(struct hisi_qm *qm, u8 cmd, dma_addr_t dma_addr, u16 queue,
507 dev_dbg(&qm->pdev->dev, "QM mailbox request to q%u: %u-%llx\n",
518 mutex_lock(&qm->mailbox_lock);
520 if (unlikely(qm_wait_mb_ready(qm))) {
522 dev_err(&qm->pdev->dev, "QM mailbox is busy to start!\n");
526 qm_mb_write(qm, &mailbox);
528 if (unlikely(qm_wait_mb_ready(qm))) {
530 dev_err(&qm->pdev->dev, "QM mailbox operation timeout!\n");
535 mutex_unlock(&qm->mailbox_lock);
538 atomic64_inc(&qm->debug.dfx.mb_err_cnt);
542 static void qm_db_v1(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
550 writeq(doorbell, qm->io_base + QM_DOORBELL_BASE_V1);
553 static void qm_db_v2(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
569 writeq(doorbell, qm->io_base + dbase);
572 static void qm_db(struct hisi_qm *qm, u16 qn, u8 cmd, u16 index, u8 priority)
574 dev_dbg(&qm->pdev->dev, "QM doorbell request: qn=%u, cmd=%u, index=%u\n",
577 qm->ops->qm_db(qm, qn, cmd, index, priority);
580 static int qm_dev_mem_reset(struct hisi_qm *qm)
584 writel(0x1, qm->io_base + QM_MEM_START_INIT);
585 return readl_relaxed_poll_timeout(qm->io_base + QM_MEM_INIT_DONE, val,
589 static u32 qm_get_irq_num_v1(struct hisi_qm *qm)
594 static u32 qm_get_irq_num_v2(struct hisi_qm *qm)
596 if (qm->fun_type == QM_HW_PF)
602 static struct hisi_qp *qm_to_hisi_qp(struct hisi_qm *qm, struct qm_eqe *eqe)
606 return &qm->qp_array[cqn];
619 static void qm_poll_qp(struct hisi_qp *qp, struct hisi_qm *qm)
631 qp->req_cb(qp, qp->sqe + qm->sqe_size *
635 qm_db(qm, qp->qp_id, QM_DOORBELL_CMD_CQ,
641 qm_db(qm, qp->qp_id, QM_DOORBELL_CMD_CQ,
648 struct hisi_qm *qm = container_of(work, struct hisi_qm, work);
649 struct qm_eqe *eqe = qm->eqe + qm->status.eq_head;
653 while (QM_EQE_PHASE(eqe) == qm->status.eqc_phase) {
655 qp = qm_to_hisi_qp(qm, eqe);
656 qm_poll_qp(qp, qm);
658 if (qm->status.eq_head == QM_EQ_DEPTH - 1) {
659 qm->status.eqc_phase = !qm->status.eqc_phase;
660 eqe = qm->eqe;
661 qm->status.eq_head = 0;
664 qm->status.eq_head++;
669 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
673 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
678 struct hisi_qm *qm = (struct hisi_qm *)data;
681 if (qm->wq)
682 queue_work(qm->wq, &qm->work);
684 schedule_work(&qm->work);
691 struct hisi_qm *qm = data;
693 if (readl(qm->io_base + QM_VF_EQ_INT_SOURCE))
696 atomic64_inc(&qm->debug.dfx.err_irq_cnt);
697 dev_err(&qm->pdev->dev, "invalid int source\n");
698 qm_db(qm, 0, QM_DOORBELL_CMD_EQ, qm->status.eq_head, 0);
705 struct hisi_qm *qm = data;
706 struct qm_aeqe *aeqe = qm->aeqe + qm->status.aeq_head;
709 atomic64_inc(&qm->debug.dfx.aeq_irq_cnt);
710 if (!readl(qm->io_base + QM_VF_AEQ_INT_SOURCE))
713 while (QM_AEQE_PHASE(aeqe) == qm->status.aeqc_phase) {
716 dev_err(&qm->pdev->dev, "%s overflow\n",
719 dev_err(&qm->pdev->dev, "unknown error type %d\n",
722 if (qm->status.aeq_head == QM_Q_DEPTH - 1) {
723 qm->status.aeqc_phase = !qm->status.aeqc_phase;
724 aeqe = qm->aeqe;
725 qm->status.aeq_head = 0;
728 qm->status.aeq_head++;
731 qm_db(qm, 0, QM_DOORBELL_CMD_AEQ, qm->status.aeq_head, 0);
737 static void qm_irq_unregister(struct hisi_qm *qm)
739 struct pci_dev *pdev = qm->pdev;
741 free_irq(pci_irq_vector(pdev, QM_EQ_EVENT_IRQ_VECTOR), qm);
743 if (qm->ver == QM_HW_V1)
746 free_irq(pci_irq_vector(pdev, QM_AEQ_EVENT_IRQ_VECTOR), qm);
748 if (qm->fun_type == QM_HW_PF)
750 QM_ABNORMAL_EVENT_IRQ_VECTOR), qm);
763 static void qm_vft_data_cfg(struct hisi_qm *qm, enum vft_type type, u32 base,
771 if (qm->ver == QM_HW_V1) {
784 if (qm->ver == QM_HW_V1) {
796 writel(lower_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_L);
797 writel(upper_32_bits(tmp), qm->io_base + QM_VFT_CFG_DATA_H);
800 static int qm_set_vft_common(struct hisi_qm *qm, enum vft_type type,
806 ret = readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
811 writel(0x0, qm->io_base + QM_VFT_CFG_OP_WR);
812 writel(type, qm->io_base + QM_VFT_CFG_TYPE);
813 writel(fun_num, qm->io_base + QM_VFT_CFG);
815 qm_vft_data_cfg(qm, type, base, number);
817 writel(0x0, qm->io_base + QM_VFT_CFG_RDY);
818 writel(0x1, qm->io_base + QM_VFT_CFG_OP_ENABLE);
820 return readl_relaxed_poll_timeout(qm->io_base + QM_VFT_CFG_RDY, val,
825 static int qm_set_sqc_cqc_vft(struct hisi_qm *qm, u32 fun_num, u32 base,
831 ret = qm_set_vft_common(qm, i, fun_num, base, number);
839 static int qm_get_vft_v2(struct hisi_qm *qm, u32 *base, u32 *number)
844 ret = qm_mb(qm, QM_MB_CMD_SQC_VFT_V2, 0, 0, 1);
848 sqc_vft = readl(qm->io_base + QM_MB_CMD_DATA_ADDR_L) |
849 ((u64)readl(qm->io_base + QM_MB_CMD_DATA_ADDR_H) << 32);
866 struct hisi_qm *qm = file_to_qm(file);
868 return readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) >> QM_DFX_QN_SHIFT;
873 struct hisi_qm *qm = file_to_qm(file);
876 if (val >= qm->debug.curr_qm_qp_num)
880 (readl(qm->io_base + QM_DFX_SQE_CNT_VF_SQN) & CURRENT_FUN_MASK);
881 writel(tmp, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
884 (readl(qm->io_base + QM_DFX_CQE_CNT_VF_CQN) & CURRENT_FUN_MASK);
885 writel(tmp, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
892 struct hisi_qm *qm = file_to_qm(file);
894 return readl(qm->io_base + QM_DFX_CNT_CLR_CE);
900 struct hisi_qm *qm = file_to_qm(file);
905 writel(rd_clr_ctrl, qm->io_base + QM_DFX_CNT_CLR_CE);
1034 struct hisi_qm *qm = s->private;
1038 if (qm->fun_type == QM_HW_PF)
1044 val = readl(qm->io_base + regs->reg_offset);
1066 static void *qm_ctx_alloc(struct hisi_qm *qm, size_t ctx_size,
1069 struct device *dev = &qm->pdev->dev;
1086 static void qm_ctx_free(struct hisi_qm *qm, size_t ctx_size,
1089 struct device *dev = &qm->pdev->dev;
1095 static int dump_show(struct hisi_qm *qm, void *info,
1098 struct device *dev = &qm->pdev->dev;
1130 static int qm_dump_sqc_raw(struct hisi_qm *qm, dma_addr_t dma_addr, u16 qp_id)
1132 return qm_mb(qm, QM_MB_CMD_SQC, dma_addr, qp_id, 1);
1135 static int qm_dump_cqc_raw(struct hisi_qm *qm, dma_addr_t dma_addr, u16 qp_id)
1137 return qm_mb(qm, QM_MB_CMD_CQC, dma_addr, qp_id, 1);
1140 static int qm_sqc_dump(struct hisi_qm *qm, const char *s)
1142 struct device *dev = &qm->pdev->dev;
1152 if (ret || qp_id >= qm->qp_num) {
1153 dev_err(dev, "Please input qp num (0-%d)", qm->qp_num - 1);
1157 sqc = qm_ctx_alloc(qm, sizeof(*sqc), &sqc_dma);
1161 ret = qm_dump_sqc_raw(qm, sqc_dma, qp_id);
1163 down_read(&qm->qps_lock);
1164 if (qm->sqc) {
1165 sqc_curr = qm->sqc + qp_id;
1167 ret = dump_show(qm, sqc_curr, sizeof(*sqc),
1172 up_read(&qm->qps_lock);
1177 ret = dump_show(qm, sqc, sizeof(*sqc), "SQC");
1182 qm_ctx_free(qm, sizeof(*sqc), sqc, &sqc_dma);
1186 static int qm_cqc_dump(struct hisi_qm *qm, const char *s)
1188 struct device *dev = &qm->pdev->dev;
1198 if (ret || qp_id >= qm->qp_num) {
1199 dev_err(dev, "Please input qp num (0-%d)", qm->qp_num - 1);
1203 cqc = qm_ctx_alloc(qm, sizeof(*cqc), &cqc_dma);
1207 ret = qm_dump_cqc_raw(qm, cqc_dma, qp_id);
1209 down_read(&qm->qps_lock);
1210 if (qm->cqc) {
1211 cqc_curr = qm->cqc + qp_id;
1213 ret = dump_show(qm, cqc_curr, sizeof(*cqc),
1218 up_read(&qm->qps_lock);
1223 ret = dump_show(qm, cqc, sizeof(*cqc), "CQC");
1228 qm_ctx_free(qm, sizeof(*cqc), cqc, &cqc_dma);
1232 static int qm_eqc_aeqc_dump(struct hisi_qm *qm, char *s, size_t size,
1235 struct device *dev = &qm->pdev->dev;
1245 xeqc = qm_ctx_alloc(qm, size, &xeqc_dma);
1249 ret = qm_mb(qm, cmd, xeqc_dma, 0, 1);
1253 ret = dump_show(qm, xeqc, size, name);
1258 qm_ctx_free(qm, size, xeqc, &xeqc_dma);
1262 static int q_dump_param_parse(struct hisi_qm *qm, char *s,
1265 struct device *dev = &qm->pdev->dev;
1266 unsigned int qp_num = qm->qp_num;
1302 static int qm_sq_dump(struct hisi_qm *qm, char *s)
1304 struct device *dev = &qm->pdev->dev;
1310 ret = q_dump_param_parse(qm, s, &sqe_id, &qp_id);
1314 sqe = kzalloc(qm->sqe_size * QM_Q_DEPTH, GFP_KERNEL);
1318 qp = &qm->qp_array[qp_id];
1319 memcpy(sqe, qp->sqe, qm->sqe_size * QM_Q_DEPTH);
1320 sqe_curr = sqe + (u32)(sqe_id * qm->sqe_size);
1321 memset(sqe_curr + qm->debug.sqe_mask_offset, QM_SQE_ADDR_MASK,
1322 qm->debug.sqe_mask_len);
1324 ret = dump_show(qm, sqe_curr, qm->sqe_size, "SQE");
1333 static int qm_cq_dump(struct hisi_qm *qm, char *s)
1335 struct device *dev = &qm->pdev->dev;
1341 ret = q_dump_param_parse(qm, s, &cqe_id, &qp_id);
1345 qp = &qm->qp_array[qp_id];
1347 ret = dump_show(qm, cqe_curr, sizeof(struct qm_cqe), "CQE");
1354 static int qm_eq_aeq_dump(struct hisi_qm *qm, const char *s,
1357 struct device *dev = &qm->pdev->dev;
1377 down_read(&qm->qps_lock);
1379 if (qm->eqe && !strcmp(name, "EQE")) {
1380 xeqe = qm->eqe + xeqe_id;
1381 } else if (qm->aeqe && !strcmp(name, "AEQE")) {
1382 xeqe = qm->aeqe + xeqe_id;
1388 ret = dump_show(qm, xeqe, size, name);
1393 up_read(&qm->qps_lock);
1397 static int qm_dbg_help(struct hisi_qm *qm, char *s)
1399 struct device *dev = &qm->pdev->dev;
1419 static int qm_cmd_write_dump(struct hisi_qm *qm, const char *cmd_buf)
1421 struct device *dev = &qm->pdev->dev;
1437 ret = qm_sqc_dump(qm, s);
1439 ret = qm_cqc_dump(qm, s);
1441 ret = qm_eqc_aeqc_dump(qm, s, sizeof(struct qm_eqc),
1444 ret = qm_eqc_aeqc_dump(qm, s, sizeof(struct qm_aeqc),
1447 ret = qm_sq_dump(qm, s);
1449 ret = qm_cq_dump(qm, s);
1451 ret = qm_eq_aeq_dump(qm, s, sizeof(struct qm_eqe), "EQE");
1453 ret = qm_eq_aeq_dump(qm, s, sizeof(struct qm_aeqe), "AEQE");
1455 ret = qm_dbg_help(qm, s);
1471 struct hisi_qm *qm = filp->private_data;
1479 if (unlikely(atomic_read(&qm->status.flags) == QM_STOP))
1502 ret = qm_cmd_write_dump(qm, cmd_buf);
1520 static int qm_create_debugfs_file(struct hisi_qm *qm, enum qm_debug_file index)
1522 struct dentry *qm_d = qm->debug.qm_d;
1523 struct debugfs_file *file = qm->debug.files + index;
1530 file->debug = &qm->debug;
1535 static void qm_hw_error_init_v1(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe)
1537 writel(QM_ABNORMAL_INT_MASK_VALUE, qm->io_base + QM_ABNORMAL_INT_MASK);
1540 static void qm_hw_error_init_v2(struct hisi_qm *qm, u32 ce, u32 nfe, u32 fe)
1545 qm->error_mask = ce | nfe | fe;
1549 qm->io_base + QM_ABNORMAL_INT_SOURCE);
1552 writel(ce, qm->io_base + QM_RAS_CE_ENABLE);
1553 writel(QM_RAS_CE_TIMES_PER_IRQ, qm->io_base + QM_RAS_CE_THRESHOLD);
1554 writel(nfe, qm->io_base + QM_RAS_NFE_ENABLE);
1555 writel(fe, qm->io_base + QM_RAS_FE_ENABLE);
1557 irq_unmask &= readl(qm->io_base + QM_ABNORMAL_INT_MASK);
1558 writel(irq_unmask, qm->io_base + QM_ABNORMAL_INT_MASK);
1561 static void qm_hw_error_uninit_v2(struct hisi_qm *qm)
1563 writel(QM_ABNORMAL_INT_MASK_VALUE, qm->io_base + QM_ABNORMAL_INT_MASK);
1566 static void qm_log_hw_error(struct hisi_qm *qm, u32 error_status)
1569 struct device *dev = &qm->pdev->dev;
1582 reg_val = readl(qm->io_base + QM_ABNORMAL_INF01);
1586 dev_err(dev, "qm %s doorbell timeout in function %u\n",
1589 reg_val = readl(qm->io_base + QM_ABNORMAL_INF00);
1595 dev_err(dev, "qm %s fifo overflow in function %u\n",
1603 static enum acc_err_result qm_hw_error_handle_v2(struct hisi_qm *qm)
1608 tmp = readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
1609 error_status = qm->error_mask & tmp;
1613 qm->err_status.is_qm_ecc_mbit = true;
1615 qm_log_hw_error(qm, error_status);
1617 writel(error_status, qm->io_base +
1651 return qp->sqe + sq_tail * qp->qm->sqe_size;
1654 static struct hisi_qp *qm_create_qp_nolock(struct hisi_qm *qm, u8 alg_type)
1656 struct device *dev = &qm->pdev->dev;
1660 if (!qm_qp_avail_state(qm, NULL, QP_INIT))
1663 if (qm->qp_in_used == qm->qp_num) {
1665 qm->qp_num);
1666 atomic64_inc(&qm->debug.dfx.create_qp_err_cnt);
1670 qp_id = idr_alloc_cyclic(&qm->qp_idr, NULL, 0, qm->qp_num, GFP_ATOMIC);
1673 qm->qp_num);
1674 atomic64_inc(&qm->debug.dfx.create_qp_err_cnt);
1678 qp = &qm->qp_array[qp_id];
1686 qm->qp_in_used++;
1693 * hisi_qm_create_qp() - Create a queue pair from qm.
1694 * @qm: The qm we create a qp from.
1697 * return created qp, -EBUSY if all qps in qm allocated, -ENOMEM if allocating
1700 struct hisi_qp *hisi_qm_create_qp(struct hisi_qm *qm, u8 alg_type)
1704 down_write(&qm->qps_lock);
1705 qp = qm_create_qp_nolock(qm, alg_type);
1706 up_write(&qm->qps_lock);
1713 * hisi_qm_release_qp() - Release a qp back to its qm.
1720 struct hisi_qm *qm = qp->qm;
1722 down_write(&qm->qps_lock);
1724 if (!qm_qp_avail_state(qm, qp, QP_CLOSE)) {
1725 up_write(&qm->qps_lock);
1729 qm->qp_in_used--;
1730 idr_remove(&qm->qp_idr, qp->qp_id);
1732 up_write(&qm->qps_lock);
1738 struct hisi_qm *qm = qp->qm;
1739 struct device *dev = &qm->pdev->dev;
1740 enum qm_hw_ver ver = qm->ver;
1761 sqc->dw3 = cpu_to_le32(QM_MK_SQC_DW3_V1(0, 0, 0, qm->sqe_size));
1764 sqc->dw3 = cpu_to_le32(QM_MK_SQC_DW3_V2(qm->sqe_size));
1770 ret = qm_mb(qm, QM_MB_CMD_SQC, sqc_dma, qp_id, 0);
1796 ret = qm_mb(qm, QM_MB_CMD_CQC, cqc_dma, qp_id, 0);
1805 struct hisi_qm *qm = qp->qm;
1806 struct device *dev = &qm->pdev->dev;
1811 if (!qm_qp_avail_state(qm, qp, QP_START))
1834 struct hisi_qm *qm = qp->qm;
1837 down_write(&qm->qps_lock);
1839 up_write(&qm->qps_lock);
1852 struct hisi_qm *qm = qp->qm;
1853 struct device *dev = &qm->pdev->dev;
1864 if (qm->err_status.is_qm_ecc_mbit || qm->err_status.is_dev_ecc_mbit)
1867 addr = qm_ctx_alloc(qm, size, &dma_addr);
1874 ret = qm_dump_sqc_raw(qm, dma_addr, qp->qp_id);
1881 ret = qm_dump_cqc_raw(qm, (dma_addr + sizeof(struct qm_sqc)),
1902 qm_ctx_free(qm, size, addr, &dma_addr);
1909 struct device *dev = &qp->qm->pdev->dev;
1923 if (!qm_qp_avail_state(qp->qm, qp, QP_STOP))
1932 if (qp->qm->wq)
1933 flush_workqueue(qp->qm->wq);
1935 flush_work(&qp->qm->work);
1943 * hisi_qm_stop_qp() - Stop a qp in qm.
1952 down_write(&qp->qm->qps_lock);
1954 up_write(&qp->qm->qps_lock);
1966 * if qp related qm is resetting.
1983 atomic_read(&qp->qm->status.flags) == QM_STOP ||
1985 dev_info_ratelimited(&qp->qm->pdev->dev, "QP is stopped or resetting\n");
1992 memcpy(sqe, msg, qp->qm->sqe_size);
1994 qm_db(qp->qm, qp->qp_id, QM_DOORBELL_CMD_SQ, sq_tail_next, 0);
2002 static void hisi_qm_cache_wb(struct hisi_qm *qm)
2006 if (qm->ver == QM_HW_V1)
2009 writel(0x1, qm->io_base + QM_CACHE_WB_START);
2010 if (readl_relaxed_poll_timeout(qm->io_base + QM_CACHE_WB_DONE,
2012 dev_err(&qm->pdev->dev, "QM writeback sqc cache fail!\n");
2029 struct hisi_qm *qm = uacce->priv;
2033 qp = hisi_qm_create_qp(qm, alg_type);
2050 hisi_qm_cache_wb(qp->qm);
2060 struct hisi_qm *qm = qp->qm;
2062 struct pci_dev *pdev = qm->pdev;
2069 if (qm->ver == QM_HW_V1) {
2081 qm->phys_base >> PAGE_SHIFT,
2117 struct hisi_qm *qm = q->uacce->priv;
2120 down_write(&qm->qps_lock);
2122 up_write(&qm->qps_lock);
2164 static int qm_alloc_uacce(struct hisi_qm *qm)
2166 struct pci_dev *pdev = qm->pdev;
2186 qm->use_sva = true;
2190 qm->uacce = NULL;
2195 uacce->priv = qm;
2196 uacce->algs = qm->algs;
2198 if (qm->ver == QM_HW_V1) {
2207 dus_page_nr = (PAGE_SIZE - 1 + qm->sqe_size * QM_Q_DEPTH +
2213 qm->uacce = uacce;
2221 * @qm: The qm needed to be fronzen.
2225 static int qm_frozen(struct hisi_qm *qm)
2227 down_write(&qm->qps_lock);
2229 if (qm->is_frozen) {
2230 up_write(&qm->qps_lock);
2234 if (!qm->qp_in_used) {
2235 qm->qp_in_used = qm->qp_num;
2236 qm->is_frozen = true;
2237 up_write(&qm->qps_lock);
2241 up_write(&qm->qps_lock);
2249 struct hisi_qm *qm, *vf_qm;
2258 list_for_each_entry(qm, &qm_list->list, list) {
2259 dev = qm->pdev;
2279 * @qm: The qm needed to wait for the task to finish.
2282 void hisi_qm_wait_task_finish(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
2284 while (qm_frozen(qm) ||
2285 ((qm->fun_type == QM_HW_PF) &&
2286 qm_try_frozen_vfs(qm->pdev, qm_list))) {
2295 * hisi_qm_get_free_qp_num() - Get free number of qp in qm.
2296 * @qm: The qm which want to get free qp.
2298 * This function return free number of qp in qm.
2300 int hisi_qm_get_free_qp_num(struct hisi_qm *qm)
2304 down_read(&qm->qps_lock);
2305 ret = qm->qp_num - qm->qp_in_used;
2306 up_read(&qm->qps_lock);
2312 static void hisi_qp_memory_uninit(struct hisi_qm *qm, int num)
2314 struct device *dev = &qm->pdev->dev;
2319 qdma = &qm->qp_array[i].qdma;
2323 kfree(qm->qp_array);
2326 static int hisi_qp_memory_init(struct hisi_qm *qm, size_t dma_size, int id)
2328 struct device *dev = &qm->pdev->dev;
2329 size_t off = qm->sqe_size * QM_Q_DEPTH;
2332 qp = &qm->qp_array[id];
2343 qp->qm = qm;
2349 static int hisi_qm_memory_init(struct hisi_qm *qm)
2351 struct device *dev = &qm->pdev->dev;
2355 #define QM_INIT_BUF(qm, type, num) do { \
2356 (qm)->type = ((qm)->qdma.va + (off)); \
2357 (qm)->type##_dma = (qm)->qdma.dma + (off); \
2361 idr_init(&qm->qp_idr);
2362 qm->qdma.size = QMC_ALIGN(sizeof(struct qm_eqe) * QM_EQ_DEPTH) +
2364 QMC_ALIGN(sizeof(struct qm_sqc) * qm->qp_num) +
2365 QMC_ALIGN(sizeof(struct qm_cqc) * qm->qp_num);
2366 qm->qdma.va = dma_alloc_coherent(dev, qm->qdma.size, &qm->qdma.dma,
2368 dev_dbg(dev, "allocate qm dma buf size=%zx)\n", qm->qdma.size);
2369 if (!qm->qdma.va)
2372 QM_INIT_BUF(qm, eqe, QM_EQ_DEPTH);
2373 QM_INIT_BUF(qm, aeqe, QM_Q_DEPTH);
2374 QM_INIT_BUF(qm, sqc, qm->qp_num);
2375 QM_INIT_BUF(qm, cqc, qm->qp_num);
2377 qm->qp_array = kcalloc(qm->qp_num, sizeof(struct hisi_qp), GFP_KERNEL);
2378 if (!qm->qp_array) {
2384 qp_dma_size = qm->sqe_size * QM_Q_DEPTH +
2387 for (i = 0; i < qm->qp_num; i++) {
2388 ret = hisi_qp_memory_init(qm, qp_dma_size, i);
2398 hisi_qp_memory_uninit(qm, i);
2400 dma_free_coherent(dev, qm->qdma.size, qm->qdma.va, qm->qdma.dma);
2405 static void hisi_qm_pre_init(struct hisi_qm *qm)
2407 struct pci_dev *pdev = qm->pdev;
2409 if (qm->ver == QM_HW_V1)
2410 qm->ops = &qm_hw_ops_v1;
2412 qm->ops = &qm_hw_ops_v2;
2414 pci_set_drvdata(pdev, qm);
2415 mutex_init(&qm->mailbox_lock);
2416 init_rwsem(&qm->qps_lock);
2417 qm->qp_in_used = 0;
2418 qm->is_frozen = false;
2422 * hisi_qm_uninit() - Uninitialize qm.
2423 * @qm: The qm needed uninit.
2425 * This function uninits qm related device resources.
2427 void hisi_qm_uninit(struct hisi_qm *qm)
2429 struct pci_dev *pdev = qm->pdev;
2432 down_write(&qm->qps_lock);
2434 if (!qm_avail_state(qm, QM_CLOSE)) {
2435 up_write(&qm->qps_lock);
2439 uacce_remove(qm->uacce);
2440 qm->uacce = NULL;
2442 hisi_qp_memory_uninit(qm, qm->qp_num);
2443 idr_destroy(&qm->qp_idr);
2445 if (qm->qdma.va) {
2446 hisi_qm_cache_wb(qm);
2447 dma_free_coherent(dev, qm->qdma.size,
2448 qm->qdma.va, qm->qdma.dma);
2449 memset(&qm->qdma, 0, sizeof(qm->qdma));
2452 qm_irq_unregister(qm);
2454 iounmap(qm->io_base);
2458 up_write(&qm->qps_lock);
2463 * hisi_qm_get_vft() - Get vft from a qm.
2464 * @qm: The qm we want to get its vft.
2468 * We can allocate multiple queues to a qm by configuring virtual function
2472 * qm hw v1 does not support this interface.
2474 int hisi_qm_get_vft(struct hisi_qm *qm, u32 *base, u32 *number)
2479 if (!qm->ops->get_vft) {
2480 dev_err(&qm->pdev->dev, "Don't support vft read!\n");
2484 return qm->ops->get_vft(qm, base, number);
2492 * Assign queues A~B to PF: hisi_qm_set_vft(qm, 0, A, B - A + 1)
2493 * Assign queues A~B to VF: hisi_qm_set_vft(qm, 2, A, B - A + 1)
2496 static int hisi_qm_set_vft(struct hisi_qm *qm, u32 fun_num, u32 base,
2499 u32 max_q_num = qm->ctrl_qp_num;
2505 return qm_set_sqc_cqc_vft(qm, fun_num, base, number);
2508 static void qm_init_eq_aeq_status(struct hisi_qm *qm)
2510 struct hisi_qm_status *status = &qm->status;
2518 static int qm_eq_ctx_cfg(struct hisi_qm *qm)
2520 struct device *dev = &qm->pdev->dev;
2527 qm_init_eq_aeq_status(qm);
2539 eqc->base_l = cpu_to_le32(lower_32_bits(qm->eqe_dma));
2540 eqc->base_h = cpu_to_le32(upper_32_bits(qm->eqe_dma));
2541 if (qm->ver == QM_HW_V1)
2544 ret = qm_mb(qm, QM_MB_CMD_EQC, eqc_dma, 0, 0);
2560 aeqc->base_l = cpu_to_le32(lower_32_bits(qm->aeqe_dma));
2561 aeqc->base_h = cpu_to_le32(upper_32_bits(qm->aeqe_dma));
2564 ret = qm_mb(qm, QM_MB_CMD_AEQC, aeqc_dma, 0, 0);
2571 static int __hisi_qm_start(struct hisi_qm *qm)
2575 WARN_ON(!qm->qdma.dma);
2577 if (qm->fun_type == QM_HW_PF) {
2578 ret = qm_dev_mem_reset(qm);
2582 ret = hisi_qm_set_vft(qm, 0, qm->qp_base, qm->qp_num);
2587 ret = qm_eq_ctx_cfg(qm);
2591 ret = qm_mb(qm, QM_MB_CMD_SQC_BT, qm->sqc_dma, 0, 0);
2595 ret = qm_mb(qm, QM_MB_CMD_CQC_BT, qm->cqc_dma, 0, 0);
2599 writel(0x0, qm->io_base + QM_VF_EQ_INT_MASK);
2600 writel(0x0, qm->io_base + QM_VF_AEQ_INT_MASK);
2606 * hisi_qm_start() - start qm
2607 * @qm: The qm to be started.
2609 * This function starts a qm, then we can allocate qp from this qm.
2611 int hisi_qm_start(struct hisi_qm *qm)
2613 struct device *dev = &qm->pdev->dev;
2616 down_write(&qm->qps_lock);
2618 if (!qm_avail_state(qm, QM_START)) {
2619 up_write(&qm->qps_lock);
2623 dev_dbg(dev, "qm start with %d queue pairs\n", qm->qp_num);
2625 if (!qm->qp_num) {
2631 ret = __hisi_qm_start(qm);
2633 atomic_set(&qm->status.flags, QM_START);
2636 up_write(&qm->qps_lock);
2641 static int qm_restart(struct hisi_qm *qm)
2643 struct device *dev = &qm->pdev->dev;
2647 ret = hisi_qm_start(qm);
2651 down_write(&qm->qps_lock);
2652 for (i = 0; i < qm->qp_num; i++) {
2653 qp = &qm->qp_array[i];
2660 up_write(&qm->qps_lock);
2666 up_write(&qm->qps_lock);
2672 static int qm_stop_started_qp(struct hisi_qm *qm)
2674 struct device *dev = &qm->pdev->dev;
2678 for (i = 0; i < qm->qp_num; i++) {
2679 qp = &qm->qp_array[i];
2694 * This function clears all queues memory in a qm. Reset of accelerator can
2697 static void qm_clear_queues(struct hisi_qm *qm)
2702 for (i = 0; i < qm->qp_num; i++) {
2703 qp = &qm->qp_array[i];
2708 memset(qm->qdma.va, 0, qm->qdma.size);
2712 * hisi_qm_stop() - Stop a qm.
2713 * @qm: The qm which will be stopped.
2714 * @r: The reason to stop qm.
2716 * This function stops qm and its qps, then qm can not accept request.
2718 * to let qm start again.
2720 int hisi_qm_stop(struct hisi_qm *qm, enum qm_stop_reason r)
2722 struct device *dev = &qm->pdev->dev;
2725 down_write(&qm->qps_lock);
2727 qm->status.stop_reason = r;
2728 if (!qm_avail_state(qm, QM_STOP)) {
2733 if (qm->status.stop_reason == QM_SOFT_RESET ||
2734 qm->status.stop_reason == QM_FLR) {
2735 ret = qm_stop_started_qp(qm);
2743 writel(0x1, qm->io_base + QM_VF_EQ_INT_MASK);
2744 writel(0x1, qm->io_base + QM_VF_AEQ_INT_MASK);
2746 if (qm->fun_type == QM_HW_PF) {
2747 ret = hisi_qm_set_vft(qm, 0, 0, 0);
2755 qm_clear_queues(qm);
2756 atomic_set(&qm->status.flags, QM_STOP);
2759 up_write(&qm->qps_lock);
2767 struct hisi_qm *qm = filp->private_data;
2771 val = atomic_read(&qm->status.flags);
2804 * hisi_qm_debug_init() - Initialize qm related debugfs files.
2805 * @qm: The qm for which we want to add debugfs files.
2807 * Create qm related debugfs files.
2809 int hisi_qm_debug_init(struct hisi_qm *qm)
2811 struct qm_dfx *dfx = &qm->debug.dfx;
2816 qm_d = debugfs_create_dir("qm", qm->debug.debug_root);
2817 qm->debug.qm_d = qm_d;
2820 if (qm->fun_type == QM_HW_PF)
2822 if (qm_create_debugfs_file(qm, i)) {
2827 debugfs_create_file("regs", 0444, qm->debug.qm_d, qm, &qm_regs_fops);
2829 debugfs_create_file("cmd", 0444, qm->debug.qm_d, qm, &qm_cmd_fops);
2831 debugfs_create_file("status", 0444, qm->debug.qm_d, qm,
2851 * hisi_qm_debug_regs_clear() - clear qm debug related registers.
2852 * @qm: The qm for which we want to clear its debug registers.
2854 void hisi_qm_debug_regs_clear(struct hisi_qm *qm)
2860 writel(0x0, qm->io_base + QM_DFX_SQE_CNT_VF_SQN);
2861 writel(0x0, qm->io_base + QM_DFX_CQE_CNT_VF_CQN);
2867 writel(0x1, qm->io_base + QM_DFX_CNT_CLR_CE);
2871 readl(qm->io_base + regs->reg_offset);
2875 writel(0x0, qm->io_base + QM_DFX_CNT_CLR_CE);
2879 static void qm_hw_error_init(struct hisi_qm *qm)
2881 const struct hisi_qm_err_info *err_info = &qm->err_ini->err_info;
2883 if (!qm->ops->hw_error_init) {
2884 dev_err(&qm->pdev->dev, "QM doesn't support hw error handling!\n");
2888 qm->ops->hw_error_init(qm, err_info->ce, err_info->nfe, err_info->fe);
2891 static void qm_hw_error_uninit(struct hisi_qm *qm)
2893 if (!qm->ops->hw_error_uninit) {
2894 dev_err(&qm->pdev->dev, "Unexpected QM hw error uninit!\n");
2898 qm->ops->hw_error_uninit(qm);
2901 static enum acc_err_result qm_hw_error_handle(struct hisi_qm *qm)
2903 if (!qm->ops->hw_error_handle) {
2904 dev_err(&qm->pdev->dev, "QM doesn't support hw error report!\n");
2908 return qm->ops->hw_error_handle(qm);
2913 * @qm: The qm for which we want to do error initialization.
2917 void hisi_qm_dev_err_init(struct hisi_qm *qm)
2919 if (qm->fun_type == QM_HW_VF)
2922 qm_hw_error_init(qm);
2924 if (!qm->err_ini->hw_err_enable) {
2925 dev_err(&qm->pdev->dev, "Device doesn't support hw error init!\n");
2928 qm->err_ini->hw_err_enable(qm);
2934 * @qm: The qm for which we want to do error uninitialization.
2938 void hisi_qm_dev_err_uninit(struct hisi_qm *qm)
2940 if (qm->fun_type == QM_HW_VF)
2943 qm_hw_error_uninit(qm);
2945 if (!qm->err_ini->hw_err_disable) {
2946 dev_err(&qm->pdev->dev, "Unexpected device hw error uninit!\n");
2949 qm->err_ini->hw_err_disable(qm);
2984 struct hisi_qm *qm;
2989 list_for_each_entry(qm, &qm_list->list, list) {
2990 dev = &qm->pdev->dev;
3002 res->qm = qm;
3048 qps[i] = hisi_qm_create_qp(tmp->qm, alg_type);
3072 static int qm_vf_q_assign(struct hisi_qm *qm, u32 num_vfs)
3075 u32 q_base = qm->qp_num;
3081 remain_q_num = qm->ctrl_qp_num - qm->qp_num;
3084 if (qm->ctrl_qp_num < qm->qp_num || remain_q_num < num_vfs)
3091 ret = hisi_qm_set_vft(qm, i, q_base, q_num);
3094 hisi_qm_set_vft(qm, j, 0, 0);
3103 static int qm_clear_vft_config(struct hisi_qm *qm)
3108 for (i = 1; i <= qm->vfs_num; i++) {
3109 ret = hisi_qm_set_vft(qm, i, 0, 0);
3113 qm->vfs_num = 0;
3129 struct hisi_qm *qm = pci_get_drvdata(pdev);
3141 ret = qm_vf_q_assign(qm, num_vfs);
3147 qm->vfs_num = num_vfs;
3152 qm_clear_vft_config(qm);
3171 struct hisi_qm *qm = pci_get_drvdata(pdev);
3179 if (!is_frozen && qm_try_frozen_vfs(pdev, qm->qm_list)) {
3185 return qm_clear_vft_config(qm);
3205 static enum acc_err_result qm_dev_err_handle(struct hisi_qm *qm)
3209 if (!qm->err_ini->get_dev_hw_err_status) {
3210 dev_err(&qm->pdev->dev, "Device doesn't support get hw error status!\n");
3215 err_sts = qm->err_ini->get_dev_hw_err_status(qm);
3217 if (err_sts & qm->err_ini->err_info.ecc_2bits_mask)
3218 qm->err_status.is_dev_ecc_mbit = true;
3220 if (!qm->err_ini->log_dev_hw_err) {
3221 dev_err(&qm->pdev->dev, "Device doesn't support log hw error!\n");
3225 qm->err_ini->log_dev_hw_err(qm, err_sts);
3232 static enum acc_err_result qm_process_dev_error(struct hisi_qm *qm)
3236 /* log qm error */
3237 qm_ret = qm_hw_error_handle(qm);
3240 dev_ret = qm_dev_err_handle(qm);
3248 * hisi_qm_dev_err_detected() - Get device and qm error status then log it.
3253 * qm hardware error status when error occur.
3258 struct hisi_qm *qm = pci_get_drvdata(pdev);
3268 ret = qm_process_dev_error(qm);
3276 static int qm_get_hw_error_status(struct hisi_qm *qm)
3278 return readl(qm->io_base + QM_ABNORMAL_INT_STATUS);
3281 static int qm_check_req_recv(struct hisi_qm *qm)
3283 struct pci_dev *pdev = qm->pdev;
3287 writel(ACC_VENDOR_ID_VALUE, qm->io_base + QM_PEH_VENDOR_ID);
3288 ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
3296 writel(PCI_VENDOR_ID_HUAWEI, qm->io_base + QM_PEH_VENDOR_ID);
3297 ret = readl_relaxed_poll_timeout(qm->io_base + QM_PEH_VENDOR_ID, val,
3306 static int qm_set_pf_mse(struct hisi_qm *qm, bool set)
3308 struct pci_dev *pdev = qm->pdev;
3330 static int qm_set_vf_mse(struct hisi_qm *qm, bool set)
3332 struct pci_dev *pdev = qm->pdev;
3357 static int qm_set_msi(struct hisi_qm *qm, bool set)
3359 struct pci_dev *pdev = qm->pdev;
3367 if (qm->err_status.is_qm_ecc_mbit ||
3368 qm->err_status.is_dev_ecc_mbit)
3372 if (readl(qm->io_base + QM_PEH_DFX_INFO0))
3379 static int qm_vf_reset_prepare(struct hisi_qm *qm,
3382 struct hisi_qm_list *qm_list = qm->qm_list;
3383 struct pci_dev *pdev = qm->pdev;
3409 static int qm_reset_prepare_ready(struct hisi_qm *qm)
3411 struct pci_dev *pdev = qm->pdev;
3425 static int qm_controller_reset_prepare(struct hisi_qm *qm)
3427 struct pci_dev *pdev = qm->pdev;
3430 ret = qm_reset_prepare_ready(qm);
3436 if (qm->vfs_num) {
3437 ret = qm_vf_reset_prepare(qm, QM_SOFT_RESET);
3444 ret = hisi_qm_stop(qm, QM_SOFT_RESET);
3453 static void qm_dev_ecc_mbit_handle(struct hisi_qm *qm)
3457 if (!qm->err_status.is_dev_ecc_mbit &&
3458 qm->err_status.is_qm_ecc_mbit &&
3459 qm->err_ini->close_axi_master_ooo) {
3461 qm->err_ini->close_axi_master_ooo(qm);
3463 } else if (qm->err_status.is_dev_ecc_mbit &&
3464 !qm->err_status.is_qm_ecc_mbit &&
3465 !qm->err_ini->close_axi_master_ooo) {
3467 nfe_enb = readl(qm->io_base + QM_RAS_NFE_ENABLE);
3469 qm->io_base + QM_RAS_NFE_ENABLE);
3470 writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SET);
3474 static int qm_soft_reset(struct hisi_qm *qm)
3476 struct pci_dev *pdev = qm->pdev;
3481 ret = qm_check_req_recv(qm);
3485 if (qm->vfs_num) {
3486 ret = qm_set_vf_mse(qm, false);
3493 ret = qm_set_msi(qm, false);
3499 qm_dev_ecc_mbit_handle(qm);
3503 qm->io_base + ACC_MASTER_GLOBAL_CTRL);
3506 ret = readl_relaxed_poll_timeout(qm->io_base + ACC_MASTER_TRANS_RETURN,
3515 ret = qm_set_pf_mse(qm, false);
3527 qm->err_ini->err_info.acpi_rst,
3546 static int qm_vf_reset_done(struct hisi_qm *qm)
3548 struct hisi_qm_list *qm_list = qm->qm_list;
3549 struct pci_dev *pdev = qm->pdev;
3575 static int qm_get_dev_err_status(struct hisi_qm *qm)
3577 return qm->err_ini->get_dev_hw_err_status(qm);
3580 static int qm_dev_hw_init(struct hisi_qm *qm)
3582 return qm->err_ini->hw_init(qm);
3585 static void qm_restart_prepare(struct hisi_qm *qm)
3589 if (!qm->err_status.is_qm_ecc_mbit &&
3590 !qm->err_status.is_dev_ecc_mbit)
3594 value = readl(qm->io_base + ACC_AM_CFG_PORT_WR_EN);
3595 writel(value & ~qm->err_ini->err_info.msi_wr_port,
3596 qm->io_base + ACC_AM_CFG_PORT_WR_EN);
3599 value = qm_get_dev_err_status(qm) &
3600 qm->err_ini->err_info.ecc_2bits_mask;
3601 if (value && qm->err_ini->clear_dev_hw_err_status)
3602 qm->err_ini->clear_dev_hw_err_status(qm, value);
3605 writel(QM_ECC_MBIT, qm->io_base + QM_ABNORMAL_INT_SOURCE);
3608 writel(ACC_ROB_ECC_ERR_MULTPL, qm->io_base + ACC_AM_ROB_ECC_INT_STS);
3610 if (qm->err_ini->open_axi_master_ooo)
3611 qm->err_ini->open_axi_master_ooo(qm);
3614 static void qm_restart_done(struct hisi_qm *qm)
3618 if (!qm->err_status.is_qm_ecc_mbit &&
3619 !qm->err_status.is_dev_ecc_mbit)
3623 value = readl(qm->io_base + ACC_AM_CFG_PORT_WR_EN);
3624 value |= qm->err_ini->err_info.msi_wr_port;
3625 writel(value, qm->io_base + ACC_AM_CFG_PORT_WR_EN);
3627 qm->err_status.is_qm_ecc_mbit = false;
3628 qm->err_status.is_dev_ecc_mbit = false;
3631 static int qm_controller_reset_done(struct hisi_qm *qm)
3633 struct pci_dev *pdev = qm->pdev;
3636 ret = qm_set_msi(qm, true);
3642 ret = qm_set_pf_mse(qm, true);
3648 if (qm->vfs_num) {
3649 ret = qm_set_vf_mse(qm, true);
3656 ret = qm_dev_hw_init(qm);
3662 qm_restart_prepare(qm);
3664 ret = qm_restart(qm);
3670 if (qm->vfs_num) {
3671 ret = qm_vf_q_assign(qm, qm->vfs_num);
3678 ret = qm_vf_reset_done(qm);
3684 hisi_qm_dev_err_init(qm);
3685 qm_restart_done(qm);
3687 clear_bit(QM_DEV_RESET_FLAG, &qm->reset_flag);
3692 static int qm_controller_reset(struct hisi_qm *qm)
3694 struct pci_dev *pdev = qm->pdev;
3699 ret = qm_controller_reset_prepare(qm);
3703 ret = qm_soft_reset(qm);
3709 ret = qm_controller_reset_done(qm);
3727 struct hisi_qm *qm = pci_get_drvdata(pdev);
3736 ret = qm_controller_reset(qm);
3747 static int qm_check_dev_error(struct hisi_qm *qm)
3751 if (qm->fun_type == QM_HW_VF)
3754 ret = qm_get_hw_error_status(qm) & QM_ECC_MBIT;
3758 return (qm_get_dev_err_status(qm) &
3759 qm->err_ini->err_info.ecc_2bits_mask);
3765 struct hisi_qm *qm = pci_get_drvdata(pdev);
3781 ret = qm_reset_prepare_ready(qm);
3787 if (qm->vfs_num) {
3788 ret = qm_vf_reset_prepare(qm, QM_FLR);
3796 ret = hisi_qm_stop(qm, QM_FLR);
3809 struct hisi_qm *qm = pci_get_drvdata(pf_pdev);
3812 pci_read_config_dword(qm->pdev, PCI_COMMAND, &id);
3818 clear_bit(QM_DEV_RESET_FLAG, &qm->reset_flag);
3826 struct hisi_qm *qm = pci_get_drvdata(pdev);
3831 ret = qm_restart(qm);
3837 if (qm->fun_type == QM_HW_PF) {
3838 ret = qm_dev_hw_init(qm);
3844 if (!qm->vfs_num)
3847 ret = qm_vf_q_assign(qm, qm->vfs_num);
3853 ret = qm_vf_reset_done(qm);
3868 struct hisi_qm *qm = data;
3871 atomic64_inc(&qm->debug.dfx.abnormal_irq_cnt);
3872 ret = qm_process_dev_error(qm);
3874 schedule_work(&qm->rst_work);
3879 static int qm_irq_register(struct hisi_qm *qm)
3881 struct pci_dev *pdev = qm->pdev;
3885 qm_irq, IRQF_SHARED, qm->dev_name, qm);
3889 if (qm->ver != QM_HW_V1) {
3891 qm_aeq_irq, IRQF_SHARED, qm->dev_name, qm);
3895 if (qm->fun_type == QM_HW_PF) {
3899 qm->dev_name, qm);
3908 free_irq(pci_irq_vector(pdev, QM_AEQ_EVENT_IRQ_VECTOR), qm);
3910 free_irq(pci_irq_vector(pdev, QM_EQ_EVENT_IRQ_VECTOR), qm);
3918 * This function will stop qm when OS shutdown or rebooting.
3922 struct hisi_qm *qm = pci_get_drvdata(pdev);
3925 ret = hisi_qm_stop(qm, QM_NORMAL);
3927 dev_err(&pdev->dev, "Fail to stop qm in shutdown!\n");
3933 struct hisi_qm *qm = container_of(rst_work, struct hisi_qm, rst_work);
3937 ret = qm_controller_reset(qm);
3939 dev_err(&qm->pdev->dev, "controller reset failed (%d)\n", ret);
3944 * hisi_qm_alg_register() - Register alg to crypto and add qm to qm_list.
3945 * @qm: The qm needs add.
3946 * @qm_list: The qm list.
3948 * This function adds qm to qm list, and will register algorithm to
3949 * crypto when the qm list is empty.
3951 int hisi_qm_alg_register(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
3959 list_add_tail(&qm->list, &qm_list->list);
3966 list_del(&qm->list);
3976 * hisi_qm_alg_unregister() - Unregister alg from crypto and delete qm from
3977 * qm list.
3978 * @qm: The qm needs delete.
3979 * @qm_list: The qm list.
3981 * This function deletes qm from qm list, and will unregister algorithm
3982 * from crypto when the qm list is empty.
3984 void hisi_qm_alg_unregister(struct hisi_qm *qm, struct hisi_qm_list *qm_list)
3987 list_del(&qm->list);
3996 * hisi_qm_init() - Initialize configures about qm.
3997 * @qm: The qm needing init.
3999 * This function init qm, then we can call hisi_qm_start to put qm into work.
4001 int hisi_qm_init(struct hisi_qm *qm)
4003 struct pci_dev *pdev = qm->pdev;
4008 hisi_qm_pre_init(qm);
4010 ret = qm_alloc_uacce(qm);
4020 ret = pci_request_mem_regions(pdev, qm->dev_name);
4026 qm->phys_base = pci_resource_start(pdev, PCI_BAR_2);
4027 qm->phys_size = pci_resource_len(qm->pdev, PCI_BAR_2);
4028 qm->io_base = ioremap(qm->phys_base, qm->phys_size);
4029 if (!qm->io_base) {
4039 if (!qm->ops->get_irq_num) {
4043 num_vec = qm->ops->get_irq_num(qm);
4050 ret = qm_irq_register(qm);
4054 if (qm->fun_type == QM_HW_VF && qm->ver != QM_HW_V1) {
4056 ret = hisi_qm_get_vft(qm, &qm->qp_base, &qm->qp_num);
4061 ret = hisi_qm_memory_init(qm);
4065 INIT_WORK(&qm->work, qm_work_process);
4066 if (qm->fun_type == QM_HW_PF)
4067 INIT_WORK(&qm->rst_work, hisi_qm_controller_reset);
4069 atomic_set(&qm->status.flags, QM_INIT);
4074 qm_irq_unregister(qm);
4078 iounmap(qm->io_base);
4084 uacce_remove(qm->uacce);
4085 qm->uacce = NULL;