Lines Matching defs:hifn_write_1
644 static inline void hifn_write_1(struct hifn_device *dev, u32 reg, u32 val)
674 hifn_write_1(dev, HIFN_1_DMA_CSR,
678 hifn_write_1(dev, HIFN_1_DMA_IER, 0);
688 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
696 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE);
699 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MODE |
704 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
803 hifn_write_1(dev, HIFN_1_PUB_RESET, hifn_read_1(dev, HIFN_1_PUB_RESET) |
816 hifn_write_1(dev, HIFN_1_PUB_IEN, HIFN_PUBIEN_DONE);
818 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
825 hifn_write_1(dev, HIFN_1_RNG_CONFIG,
858 hifn_write_1(dev, HIFN_1_DMA_CNFG,
864 hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, 0);
869 hifn_write_1(dev, HIFN_1_UNLOCK_SECRET2, addr);
873 hifn_write_1(dev, HIFN_1_DMA_CNFG, dmacfg);
950 hifn_write_1(dev, HIFN_1_PLL, pllcfg |
957 hifn_write_1(dev, HIFN_1_PLL, pllcfg |
961 hifn_write_1(dev, HIFN_1_PLL, pllcfg |
983 hifn_write_1(dev, HIFN_1_DMA_CRAR, dptr +
985 hifn_write_1(dev, HIFN_1_DMA_SRAR, dptr +
987 hifn_write_1(dev, HIFN_1_DMA_DRAR, dptr +
989 hifn_write_1(dev, HIFN_1_DMA_RRAR, dptr +
994 hifn_write_1(dev, HIFN_1_DMA_CSR,
1008 hifn_write_1(dev, HIFN_1_DMA_CSR,
1030 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1043 hifn_write_1(dev, HIFN_1_DMA_CNFG, HIFN_DMACNFG_MSTRESET |
1095 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);
1222 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_C_CTRL_ENA);
1258 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_S_CTRL_ENA);
1285 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_R_CTRL_ENA);
1315 hifn_write_1(dev, HIFN_1_DMA_CSR, HIFN_DMACSR_D_CTRL_ENA);
1806 hifn_write_1(dev, HIFN_1_DMA_CSR, r);
1866 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & dev->dmareg);
1871 hifn_write_1(dev, HIFN_1_PUB_STATUS,
1884 hifn_write_1(dev, HIFN_1_DMA_CSR, dmacsr & (HIFN_DMACSR_R_OVER |
1904 hifn_write_1(dev, HIFN_1_DMA_IER, dev->dmareg);