Lines Matching refs:CC_REG
56 CC_REG(PERIPHERAL_ID_0), CC_REG(PERIPHERAL_ID_1),
57 CC_REG(PERIPHERAL_ID_2), CC_REG(PERIPHERAL_ID_4)
61 CC_REG(COMPONENT_ID_0), CC_REG(COMPONENT_ID_1),
62 CC_REG(COMPONENT_ID_2), CC_REG(COMPONENT_ID_3)
143 irr = cc_ioread(drvdata, CC_REG(HOST_IRR));
149 imr = cc_ioread(drvdata, CC_REG(HOST_IMR));
152 cc_iowrite(drvdata, CC_REG(HOST_ICR), irr);
160 cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | drvdata->comp_mask);
170 cc_iowrite(drvdata, CC_REG(HOST_IMR), imr | CC_GPR0_IRQ_MASK);
180 axi_err = cc_ioread(drvdata, CC_REG(AXIM_MON_ERR));
209 val = cc_ioread(drvdata, CC_REG(NVM_IS_IDLE));
229 val = cc_ioread(drvdata, CC_REG(AXIM_CFG));
230 cc_iowrite(drvdata, CC_REG(AXIM_CFG), val & ~CC_AXI_IRQ_MASK);
232 cc_ioread(drvdata, CC_REG(AXIM_CFG)));
236 val = cc_ioread(drvdata, CC_REG(HOST_IRR));
238 cc_iowrite(drvdata, CC_REG(HOST_ICR), val);
246 cc_iowrite(drvdata, CC_REG(HOST_IMR), ~val);
250 val = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS));
255 cc_iowrite(drvdata, CC_REG(AXIM_CACHE_PARAMS), cache_params);
256 val = cc_ioread(drvdata, CC_REG(AXIM_CACHE_PARAMS));
288 new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP);
289 new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_712);
290 new_drvdata->ver_offset = CC_REG(HOST_VERSION_712);
292 new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP8);
293 new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_630);
294 new_drvdata->ver_offset = CC_REG(HOST_VERSION_630);
404 val = cc_ioread(new_drvdata, CC_REG(HOST_REMOVE_INPUT_PINS));
422 val = cc_ioread(new_drvdata, CC_REG(SECURITY_DISABLED));
544 cc_iowrite(drvdata, CC_REG(HOST_IMR), 0xFFFFFFFF);