Lines Matching defs:new_drvdata
268 struct cc_drvdata *new_drvdata;
278 new_drvdata = devm_kzalloc(dev, sizeof(*new_drvdata), GFP_KERNEL);
279 if (!new_drvdata)
283 new_drvdata->hw_rev_name = hw_rev->name;
284 new_drvdata->hw_rev = hw_rev->rev;
285 new_drvdata->std_bodies = hw_rev->std_bodies;
288 new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP);
289 new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_712);
290 new_drvdata->ver_offset = CC_REG(HOST_VERSION_712);
292 new_drvdata->axim_mon_offset = CC_REG(AXIM_MON_COMP8);
293 new_drvdata->sig_offset = CC_REG(HOST_SIGNATURE_630);
294 new_drvdata->ver_offset = CC_REG(HOST_VERSION_630);
297 new_drvdata->comp_mask = CC_COMP_IRQ_MASK;
299 platform_set_drvdata(plat_dev, new_drvdata);
300 new_drvdata->plat_dev = plat_dev;
305 new_drvdata->clk = clk;
307 new_drvdata->coherent = of_dma_is_coherent(np);
313 new_drvdata->cc_base = devm_ioremap_resource(dev, req_mem_cc_regs);
314 if (IS_ERR(new_drvdata->cc_base)) {
316 return PTR_ERR(new_drvdata->cc_base);
322 &req_mem_cc_regs->start, new_drvdata->cc_base);
329 init_completion(&new_drvdata->hw_queue_avail);
349 rc = clk_prepare_enable(new_drvdata->clk);
355 new_drvdata->sec_disabled = cc_sec_disable;
368 if (!cc_wait_for_reset_completion(new_drvdata)) {
374 val = cc_ioread(new_drvdata, new_drvdata->sig_offset);
382 hw_rev_pidr = cc_ioread(new_drvdata, new_drvdata->ver_offset);
385 val = cc_read_idr(new_drvdata, pidr_0124_offsets);
394 val = cc_read_idr(new_drvdata, cidr_0123_offsets);
404 val = cc_ioread(new_drvdata, CC_REG(HOST_REMOVE_INPUT_PINS));
410 if (new_drvdata->std_bodies & CC_STD_NIST) {
412 new_drvdata->std_bodies = CC_STD_OSCCA;
422 val = cc_ioread(new_drvdata, CC_REG(SECURITY_DISABLED));
424 new_drvdata->sec_disabled |= !!val;
426 if (!new_drvdata->sec_disabled) {
427 new_drvdata->comp_mask |= CC_CPP_SM4_ABORT_MASK;
428 if (new_drvdata->std_bodies & CC_STD_NIST)
429 new_drvdata->comp_mask |= CC_CPP_AES_ABORT_MASK;
433 if (new_drvdata->sec_disabled)
441 new_drvdata);
448 rc = init_cc_regs(new_drvdata, true);
454 rc = cc_debugfs_init(new_drvdata);
460 rc = cc_fips_init(new_drvdata);
465 rc = cc_sram_mgr_init(new_drvdata);
471 new_drvdata->mlli_sram_addr =
472 cc_sram_alloc(new_drvdata, MAX_MLLI_BUFF_SIZE);
473 if (new_drvdata->mlli_sram_addr == NULL_SRAM_ADDR) {
478 rc = cc_req_mgr_init(new_drvdata);
484 rc = cc_buffer_mgr_init(new_drvdata);
491 rc = cc_cipher_alloc(new_drvdata);
498 rc = cc_hash_alloc(new_drvdata);
504 rc = cc_aead_alloc(new_drvdata);
514 cc_set_ree_fips_status(new_drvdata, true);
520 cc_hash_free(new_drvdata);
522 cc_cipher_free(new_drvdata);
524 cc_buffer_mgr_fini(new_drvdata);
526 cc_req_mgr_fini(new_drvdata);
528 cc_fips_fini(new_drvdata);
530 cc_debugfs_fini(new_drvdata);
532 fini_cc_regs(new_drvdata);
537 clk_disable_unprepare(new_drvdata->clk);