Lines Matching refs:ndev
12 * @ndev: NITROX device
14 static void emu_enable_cores(struct nitrox_device *ndev)
30 nitrox_write_csr(ndev, EMU_AE_ENABLEX(i), emu_ae.value);
31 nitrox_write_csr(ndev, EMU_SE_ENABLEX(i), emu_se.value);
37 * @ndev: NITROX device
39 void nitrox_config_emu_unit(struct nitrox_device *ndev)
47 emu_enable_cores(ndev);
58 nitrox_write_csr(ndev, offset, emu_wd_int.value);
60 nitrox_write_csr(ndev, offset, emu_ge_int.value);
64 static void reset_pkt_input_ring(struct nitrox_device *ndev, int ring)
73 pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
75 nitrox_write_csr(ndev, offset, pkt_in_ctl.value);
80 pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
88 pkt_in_cnts.value = nitrox_read_csr(ndev, offset);
89 nitrox_write_csr(ndev, offset, pkt_in_cnts.value);
93 void enable_pkt_input_ring(struct nitrox_device *ndev, int ring)
101 pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
104 nitrox_write_csr(ndev, offset, pkt_in_ctl.value);
108 pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
117 * @ndev: NITROX device
119 void nitrox_config_pkt_input_rings(struct nitrox_device *ndev)
123 for (i = 0; i < ndev->nr_queues; i++) {
124 struct nitrox_cmdq *cmdq = &ndev->pkt_inq[i];
129 reset_pkt_input_ring(ndev, i);
137 nitrox_write_csr(ndev, offset, cmdq->dma);
142 pkt_in_rsize.s.rsize = ndev->qlen;
143 nitrox_write_csr(ndev, offset, pkt_in_rsize.value);
147 nitrox_write_csr(ndev, offset, 0xffffffff);
153 nitrox_write_csr(ndev, offset, pkt_in_dbell.value);
156 enable_pkt_input_ring(ndev, i);
160 static void reset_pkt_solicit_port(struct nitrox_device *ndev, int port)
169 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
171 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);
177 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
185 pkt_slc_cnts.value = nitrox_read_csr(ndev, offset);
186 nitrox_write_csr(ndev, offset, pkt_slc_cnts.value);
190 void enable_pkt_solicit_port(struct nitrox_device *ndev, int port)
206 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);
210 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
217 static void config_pkt_solicit_port(struct nitrox_device *ndev, int port)
222 reset_pkt_solicit_port(ndev, port);
229 nitrox_write_csr(ndev, offset, pkt_slc_int.value);
232 enable_pkt_solicit_port(ndev, port);
235 void nitrox_config_pkt_solicit_ports(struct nitrox_device *ndev)
239 for (i = 0; i < ndev->nr_queues; i++)
240 config_pkt_solicit_port(ndev, i);
245 * @ndev: NITROX device.
249 static void enable_nps_core_interrupts(struct nitrox_device *ndev)
260 nitrox_write_csr(ndev, NPS_CORE_INT_ENA_W1S, core_int.value);
263 void nitrox_config_nps_core_unit(struct nitrox_device *ndev)
268 nitrox_write_csr(ndev, NPS_CORE_CONTROL, 1ULL);
274 nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, core_gbl_vfcfg.value);
277 enable_nps_core_interrupts(ndev);
282 * @ndev: NITROX device.
286 static void enable_nps_pkt_interrupts(struct nitrox_device *ndev)
289 nitrox_write_csr(ndev, NPS_PKT_IN_RERR_LO_ENA_W1S, (~0ULL));
290 nitrox_write_csr(ndev, NPS_PKT_IN_RERR_HI_ENA_W1S, (~0ULL));
291 nitrox_write_csr(ndev, NPS_PKT_IN_ERR_TYPE_ENA_W1S, (~0ULL));
293 nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_HI_ENA_W1S, (~0ULL));
294 nitrox_write_csr(ndev, NPS_PKT_SLC_RERR_LO_ENA_W1S, (~0ULL));
295 nitrox_write_csr(ndev, NPS_PKT_SLC_ERR_TYPE_ENA_W1S, (~0uLL));
298 void nitrox_config_nps_pkt_unit(struct nitrox_device *ndev)
301 nitrox_config_pkt_input_rings(ndev);
302 nitrox_config_pkt_solicit_ports(ndev);
305 enable_nps_pkt_interrupts(ndev);
308 static void reset_aqm_ring(struct nitrox_device *ndev, int ring)
320 nitrox_write_csr(ndev, offset, aqmq_en_reg.value);
326 activity_stat.value = nitrox_read_csr(ndev, offset);
334 cmp_cnt.value = nitrox_read_csr(ndev, offset);
335 nitrox_write_csr(ndev, offset, cmp_cnt.value);
339 void enable_aqm_ring(struct nitrox_device *ndev, int ring)
347 nitrox_write_csr(ndev, offset, aqmq_en_reg.value);
351 void nitrox_config_aqm_rings(struct nitrox_device *ndev)
355 for (ring = 0; ring < ndev->nr_queues; ring++) {
356 struct nitrox_cmdq *cmdq = ndev->aqmq[ring];
363 reset_aqm_ring(ndev, ring);
369 nitrox_write_csr(ndev, offset, drbl.value);
375 nitrox_write_csr(ndev, offset, 0ULL);
379 nitrox_write_csr(ndev, offset, cmdq->dma);
384 qsize.host_queue_size = ndev->qlen;
385 nitrox_write_csr(ndev, offset, qsize.value);
391 nitrox_write_csr(ndev, offset, cmp_thr.value);
394 enable_aqm_ring(ndev, ring);
398 static void enable_aqm_interrupts(struct nitrox_device *ndev)
401 nitrox_write_csr(ndev, AQM_DBELL_OVF_LO_ENA_W1S, (~0ULL));
402 nitrox_write_csr(ndev, AQM_DBELL_OVF_HI_ENA_W1S, (~0ULL));
403 nitrox_write_csr(ndev, AQM_DMA_RD_ERR_LO_ENA_W1S, (~0ULL));
404 nitrox_write_csr(ndev, AQM_DMA_RD_ERR_HI_ENA_W1S, (~0ULL));
405 nitrox_write_csr(ndev, AQM_EXEC_NA_LO_ENA_W1S, (~0ULL));
406 nitrox_write_csr(ndev, AQM_EXEC_NA_HI_ENA_W1S, (~0ULL));
407 nitrox_write_csr(ndev, AQM_EXEC_ERR_LO_ENA_W1S, (~0ULL));
408 nitrox_write_csr(ndev, AQM_EXEC_ERR_HI_ENA_W1S, (~0ULL));
411 void nitrox_config_aqm_unit(struct nitrox_device *ndev)
414 nitrox_config_aqm_rings(ndev);
417 enable_aqm_interrupts(ndev);
420 void nitrox_config_pom_unit(struct nitrox_device *ndev)
428 nitrox_write_csr(ndev, POM_INT_ENA_W1S, pom_int.value);
431 for (i = 0; i < ndev->hw.se_cores; i++)
432 nitrox_write_csr(ndev, POM_PERF_CTL, BIT_ULL(i));
437 * @ndev: NITROX device
439 void nitrox_config_rand_unit(struct nitrox_device *ndev)
445 efl_rnm_ctl.value = nitrox_read_csr(ndev, offset);
448 nitrox_write_csr(ndev, offset, efl_rnm_ctl.value);
451 void nitrox_config_efl_unit(struct nitrox_device *ndev)
465 nitrox_write_csr(ndev, offset, efl_core_int.value);
468 nitrox_write_csr(ndev, offset, (~0ULL));
470 nitrox_write_csr(ndev, offset, (~0ULL));
474 void nitrox_config_bmi_unit(struct nitrox_device *ndev)
482 bmi_ctl.value = nitrox_read_csr(ndev, offset);
486 nitrox_write_csr(ndev, offset, bmi_ctl.value);
494 nitrox_write_csr(ndev, offset, bmi_int_ena.value);
497 void nitrox_config_bmo_unit(struct nitrox_device *ndev)
504 bmo_ctl2.value = nitrox_read_csr(ndev, offset);
506 nitrox_write_csr(ndev, offset, bmo_ctl2.value);
509 void invalidate_lbc(struct nitrox_device *ndev)
518 lbc_ctl.value = nitrox_read_csr(ndev, offset);
520 nitrox_write_csr(ndev, offset, lbc_ctl.value);
524 lbc_stat.value = nitrox_read_csr(ndev, offset);
531 void nitrox_config_lbc_unit(struct nitrox_device *ndev)
536 invalidate_lbc(ndev);
545 nitrox_write_csr(ndev, offset, lbc_int_ena.value);
548 nitrox_write_csr(ndev, offset, (~0ULL));
550 nitrox_write_csr(ndev, offset, (~0ULL));
553 nitrox_write_csr(ndev, offset, (~0ULL));
555 nitrox_write_csr(ndev, offset, (~0ULL));
558 void config_nps_core_vfcfg_mode(struct nitrox_device *ndev, enum vf_mode mode)
562 vfcfg.value = nitrox_read_csr(ndev, NPS_CORE_GBL_VFCFG);
565 nitrox_write_csr(ndev, NPS_CORE_GBL_VFCFG, vfcfg.value);
607 void nitrox_get_hwinfo(struct nitrox_device *ndev)
618 rst_boot.value = nitrox_read_csr(ndev, offset);
619 ndev->hw.freq = (rst_boot.pnr_mul + 3) * PLL_REF_CLK;
623 emu_fuse.value = nitrox_read_csr(ndev, offset);
626 ndev->hw.ae_cores += AE_CORES_PER_CLUSTER - dead_cores;
628 ndev->hw.se_cores += SE_CORES_PER_CLUSTER - dead_cores;
633 fus_dat1.value = nitrox_read_csr(ndev, offset);
636 ndev->hw.zip_cores = ZIP_MAX_CORES - dead_cores;
643 get_core_option(ndev->hw.se_cores, ndev->hw.ae_cores),
644 ndev->hw.freq,
645 get_feature_option(ndev->hw.zip_cores, ndev->hw.freq),
646 ndev->hw.revision_id);
649 strncpy(ndev->hw.partname, name, sizeof(ndev->hw.partname));
652 void enable_pf2vf_mbox_interrupts(struct nitrox_device *ndev)
659 nitrox_write_csr(ndev, reg_addr, value);
663 nitrox_write_csr(ndev, reg_addr, value);
666 void disable_pf2vf_mbox_interrupts(struct nitrox_device *ndev)
673 nitrox_write_csr(ndev, reg_addr, value);
677 nitrox_write_csr(ndev, reg_addr, value);