Lines Matching refs:offset
43 u64 offset;
57 offset = EMU_WD_INT_ENA_W1SX(i);
58 nitrox_write_csr(ndev, offset, emu_wd_int.value);
59 offset = EMU_GE_INT_ENA_W1SX(i);
60 nitrox_write_csr(ndev, offset, emu_ge_int.value);
69 u64 offset;
72 offset = NPS_PKT_IN_INSTR_CTLX(ring);
73 pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
75 nitrox_write_csr(ndev, offset, pkt_in_ctl.value);
80 pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
87 offset = NPS_PKT_IN_DONE_CNTSX(ring);
88 pkt_in_cnts.value = nitrox_read_csr(ndev, offset);
89 nitrox_write_csr(ndev, offset, pkt_in_cnts.value);
97 u64 offset;
100 offset = NPS_PKT_IN_INSTR_CTLX(ring);
101 pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
104 nitrox_write_csr(ndev, offset, pkt_in_ctl.value);
108 pkt_in_ctl.value = nitrox_read_csr(ndev, offset);
127 u64 offset;
136 offset = NPS_PKT_IN_INSTR_BADDRX(i);
137 nitrox_write_csr(ndev, offset, cmdq->dma);
140 offset = NPS_PKT_IN_INSTR_RSIZEX(i);
143 nitrox_write_csr(ndev, offset, pkt_in_rsize.value);
146 offset = NPS_PKT_IN_INT_LEVELSX(i);
147 nitrox_write_csr(ndev, offset, 0xffffffff);
150 offset = NPS_PKT_IN_INSTR_BAOFF_DBELLX(i);
153 nitrox_write_csr(ndev, offset, pkt_in_dbell.value);
165 u64 offset;
168 offset = NPS_PKT_SLC_CTLX(port);
169 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
171 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);
177 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
184 offset = NPS_PKT_SLC_CNTSX(port);
185 pkt_slc_cnts.value = nitrox_read_csr(ndev, offset);
186 nitrox_write_csr(ndev, offset, pkt_slc_cnts.value);
194 u64 offset;
196 offset = NPS_PKT_SLC_CTLX(port);
206 nitrox_write_csr(ndev, offset, pkt_slc_ctl.value);
210 pkt_slc_ctl.value = nitrox_read_csr(ndev, offset);
220 u64 offset;
225 offset = NPS_PKT_SLC_INT_LEVELSX(port);
229 nitrox_write_csr(ndev, offset, pkt_slc_int.value);
314 u64 offset;
317 offset = AQMQ_ENX(ring);
320 nitrox_write_csr(ndev, offset, aqmq_en_reg.value);
324 offset = AQMQ_ACTIVITY_STATX(ring);
326 activity_stat.value = nitrox_read_csr(ndev, offset);
333 offset = AQMQ_CMP_CNTX(ring);
334 cmp_cnt.value = nitrox_read_csr(ndev, offset);
335 nitrox_write_csr(ndev, offset, cmp_cnt.value);
342 u64 offset;
344 offset = AQMQ_ENX(ring);
347 nitrox_write_csr(ndev, offset, aqmq_en_reg.value);
360 u64 offset;
366 offset = AQMQ_DRBLX(ring);
369 nitrox_write_csr(ndev, offset, drbl.value);
374 offset = AQMQ_NXT_CMDX(ring);
375 nitrox_write_csr(ndev, offset, 0ULL);
378 offset = AQMQ_BADRX(ring);
379 nitrox_write_csr(ndev, offset, cmdq->dma);
382 offset = AQMQ_QSZX(ring);
385 nitrox_write_csr(ndev, offset, qsize.value);
388 offset = AQMQ_CMP_THRX(ring);
391 nitrox_write_csr(ndev, offset, cmp_thr.value);
442 u64 offset;
444 offset = EFL_RNM_CTL_STATUS;
445 efl_rnm_ctl.value = nitrox_read_csr(ndev, offset);
448 nitrox_write_csr(ndev, offset, efl_rnm_ctl.value);
457 u64 offset;
460 offset = EFL_CORE_INT_ENA_W1SX(i);
465 nitrox_write_csr(ndev, offset, efl_core_int.value);
467 offset = EFL_CORE_VF_ERR_INT0_ENA_W1SX(i);
468 nitrox_write_csr(ndev, offset, (~0ULL));
469 offset = EFL_CORE_VF_ERR_INT1_ENA_W1SX(i);
470 nitrox_write_csr(ndev, offset, (~0ULL));
478 u64 offset;
481 offset = BMI_CTL;
482 bmi_ctl.value = nitrox_read_csr(ndev, offset);
486 nitrox_write_csr(ndev, offset, bmi_ctl.value);
489 offset = BMI_INT_ENA_W1S;
494 nitrox_write_csr(ndev, offset, bmi_int_ena.value);
500 u64 offset;
503 offset = BMO_CTL2;
504 bmo_ctl2.value = nitrox_read_csr(ndev, offset);
506 nitrox_write_csr(ndev, offset, bmo_ctl2.value);
514 u64 offset;
517 offset = LBC_INVAL_CTL;
518 lbc_ctl.value = nitrox_read_csr(ndev, offset);
520 nitrox_write_csr(ndev, offset, lbc_ctl.value);
522 offset = LBC_INVAL_STATUS;
524 lbc_stat.value = nitrox_read_csr(ndev, offset);
534 u64 offset;
539 offset = LBC_INT_ENA_W1S;
545 nitrox_write_csr(ndev, offset, lbc_int_ena.value);
547 offset = LBC_PLM_VF1_64_INT_ENA_W1S;
548 nitrox_write_csr(ndev, offset, (~0ULL));
549 offset = LBC_PLM_VF65_128_INT_ENA_W1S;
550 nitrox_write_csr(ndev, offset, (~0ULL));
552 offset = LBC_ELM_VF1_64_INT_ENA_W1S;
553 nitrox_write_csr(ndev, offset, (~0ULL));
554 offset = LBC_ELM_VF65_128_INT_ENA_W1S;
555 nitrox_write_csr(ndev, offset, (~0ULL));
614 u64 offset;
617 offset = RST_BOOT;
618 rst_boot.value = nitrox_read_csr(ndev, offset);
622 offset = EMU_FUSE_MAPX(i);
623 emu_fuse.value = nitrox_read_csr(ndev, offset);
632 offset = FUS_DAT1;
633 fus_dat1.value = nitrox_read_csr(ndev, offset);