Lines Matching refs:base
113 struct atmel_aes_base_ctx base;
117 struct atmel_aes_base_ctx base;
127 struct atmel_aes_base_ctx base;
143 struct atmel_aes_base_ctx base;
150 struct atmel_aes_base_ctx base;
162 struct atmel_aes_reqctx base;
519 return container_of(ctx, struct atmel_aes_ctr_ctx, base);
1133 return atmel_aes_handle_queue(dd, &req->base);
1247 ctx->base.start = atmel_aes_start;
1257 ctx->base.start = atmel_aes_ctr_start;
1264 .base.cra_name = "ecb(aes)",
1265 .base.cra_driver_name = "atmel-ecb-aes",
1266 .base.cra_blocksize = AES_BLOCK_SIZE,
1267 .base.cra_ctxsize = sizeof(struct atmel_aes_ctx),
1277 .base.cra_name = "cbc(aes)",
1278 .base.cra_driver_name = "atmel-cbc-aes",
1279 .base.cra_blocksize = AES_BLOCK_SIZE,
1280 .base.cra_ctxsize = sizeof(struct atmel_aes_ctx),
1291 .base.cra_name = "ofb(aes)",
1292 .base.cra_driver_name = "atmel-ofb-aes",
1293 .base.cra_blocksize = AES_BLOCK_SIZE,
1294 .base.cra_ctxsize = sizeof(struct atmel_aes_ctx),
1305 .base.cra_name = "cfb(aes)",
1306 .base.cra_driver_name = "atmel-cfb-aes",
1307 .base.cra_blocksize = AES_BLOCK_SIZE,
1308 .base.cra_ctxsize = sizeof(struct atmel_aes_ctx),
1319 .base.cra_name = "cfb32(aes)",
1320 .base.cra_driver_name = "atmel-cfb32-aes",
1321 .base.cra_blocksize = CFB32_BLOCK_SIZE,
1322 .base.cra_ctxsize = sizeof(struct atmel_aes_ctx),
1333 .base.cra_name = "cfb16(aes)",
1334 .base.cra_driver_name = "atmel-cfb16-aes",
1335 .base.cra_blocksize = CFB16_BLOCK_SIZE,
1336 .base.cra_ctxsize = sizeof(struct atmel_aes_ctx),
1347 .base.cra_name = "cfb8(aes)",
1348 .base.cra_driver_name = "atmel-cfb8-aes",
1349 .base.cra_blocksize = CFB8_BLOCK_SIZE,
1350 .base.cra_ctxsize = sizeof(struct atmel_aes_ctx),
1361 .base.cra_name = "ctr(aes)",
1362 .base.cra_driver_name = "atmel-ctr-aes",
1363 .base.cra_blocksize = 1,
1364 .base.cra_ctxsize = sizeof(struct atmel_aes_ctr_ctx),
1377 .base.cra_name = "cfb64(aes)",
1378 .base.cra_driver_name = "atmel-cfb64-aes",
1379 .base.cra_blocksize = CFB64_BLOCK_SIZE,
1380 .base.cra_ctxsize = sizeof(struct atmel_aes_ctx),
1412 return container_of(ctx, struct atmel_aes_gcm_ctx, base);
1707 return atmel_aes_handle_queue(dd, &req->base);
1747 ctx->base.start = atmel_aes_gcm_start;
1761 .base = {
1775 return container_of(ctx, struct atmel_aes_xts_ctx, base);
1799 ctx->key2, ctx->base.keylen);
1852 memcpy(ctx->base.key, key, keylen/2);
1854 ctx->base.keylen = keylen/2;
1874 ctx->base.start = atmel_aes_xts_start;
1880 .base.cra_name = "xts(aes)",
1881 .base.cra_driver_name = "atmel-xts-aes",
1882 .base.cra_blocksize = AES_BLOCK_SIZE,
1883 .base.cra_ctxsize = sizeof(struct atmel_aes_xts_ctx),
1924 atmel_aes_set_mode(dd, &rctx->base);
2049 if (keys.enckeylen > sizeof(ctx->base.key))
2062 ctx->base.keylen = keys.enckeylen;
2063 memcpy(ctx->base.key, keys.enckey, keys.enckeylen);
2085 ctx->base.start = atmel_aes_authenc_start;
2145 rctx->base.mode = mode;
2153 return atmel_aes_handle_queue(dd, &req->base);
2176 .base = {
2192 .base = {
2208 .base = {
2224 .base = {
2240 .base = {
2372 atmel_aes_crypto_alg_init(&aes_algs[i].base);
2380 atmel_aes_crypto_alg_init(&aes_cfb64_alg.base);
2388 atmel_aes_crypto_alg_init(&aes_gcm_alg.base);
2396 atmel_aes_crypto_alg_init(&aes_xts_alg.base);
2406 atmel_aes_crypto_alg_init(&aes_authenc_algs[i].base);
2509 /* Get the base address */