Lines Matching refs:reg
200 void __iomem *reg = NULL;
203 reg = (dmc_base[0] + 0x30);
205 reg = (dmc_base[1] + 0x30);
220 writel_relaxed(tmp1, reg);
225 unsigned long reg;
296 reg = readl_relaxed(S5P_CLK_DIV2);
297 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
298 reg |= (3 << S5P_CLKDIV2_G3D_SHIFT) |
300 writel_relaxed(reg, S5P_CLK_DIV2);
304 reg = readl_relaxed(S5P_CLKDIV_STAT0);
305 } while (reg & ((1 << 16) | (1 << 17)));
311 reg = readl_relaxed(S5P_CLK_SRC2);
312 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
313 reg |= (1 << S5P_CLKSRC2_G3D_SHIFT) |
315 writel_relaxed(reg, S5P_CLK_SRC2);
318 reg = readl_relaxed(S5P_CLKMUX_STAT1);
319 } while (reg & ((1 << 7) | (1 << 3)));
330 reg = readl_relaxed(S5P_CLK_SRC0);
331 reg &= ~(S5P_CLKSRC0_MUX200_MASK);
332 reg |= (0x1 << S5P_CLKSRC0_MUX200_SHIFT);
333 writel_relaxed(reg, S5P_CLK_SRC0);
336 reg = readl_relaxed(S5P_CLKMUX_STAT0);
337 } while (reg & (0x1 << 18));
342 reg = readl_relaxed(S5P_CLK_DIV0);
344 reg &= ~(S5P_CLKDIV0_APLL_MASK | S5P_CLKDIV0_A2M_MASK |
349 reg |= ((clkdiv_val[index][0] << S5P_CLKDIV0_APLL_SHIFT) |
358 writel_relaxed(reg, S5P_CLK_DIV0);
361 reg = readl_relaxed(S5P_CLKDIV_STAT0);
362 } while (reg & 0xff);
365 reg = readl_relaxed(S5P_ARM_MCS_CON);
366 reg &= ~0x3;
368 reg |= 0x3;
370 reg |= 0x1;
372 writel_relaxed(reg, S5P_ARM_MCS_CON);
389 reg = readl_relaxed(S5P_APLL_CON);
390 } while (!(reg & (0x1 << 29)));
397 reg = readl_relaxed(S5P_CLK_SRC2);
398 reg &= ~(S5P_CLKSRC2_G3D_MASK | S5P_CLKSRC2_MFC_MASK);
399 reg |= (0 << S5P_CLKSRC2_G3D_SHIFT) |
401 writel_relaxed(reg, S5P_CLK_SRC2);
404 reg = readl_relaxed(S5P_CLKMUX_STAT1);
405 } while (reg & ((1 << 7) | (1 << 3)));
411 reg = readl_relaxed(S5P_CLK_DIV2);
412 reg &= ~(S5P_CLKDIV2_G3D_MASK | S5P_CLKDIV2_MFC_MASK);
413 reg |= (clkdiv_val[index][10] << S5P_CLKDIV2_G3D_SHIFT) |
415 writel_relaxed(reg, S5P_CLK_DIV2);
419 reg = readl_relaxed(S5P_CLKDIV_STAT0);
420 } while (reg & ((1 << 16) | (1 << 17)));
423 reg = readl_relaxed(S5P_CLK_SRC0);
424 reg &= ~(S5P_CLKSRC0_MUX200_MASK);
425 reg |= (0x0 << S5P_CLKSRC0_MUX200_SHIFT);
426 writel_relaxed(reg, S5P_CLK_SRC0);
429 reg = readl_relaxed(S5P_CLKMUX_STAT0);
430 } while (reg & (0x1 << 18));
446 reg = readl_relaxed(S5P_CLK_DIV6);
447 reg &= ~S5P_CLKDIV6_ONEDRAM_MASK;
448 reg |= (clkdiv_val[index][8] << S5P_CLKDIV6_ONEDRAM_SHIFT);
449 writel_relaxed(reg, S5P_CLK_DIV6);
452 reg = readl_relaxed(S5P_CLKDIV_STAT1);
453 } while (reg & (1 << 15));