Lines Matching defs:DMC1
106 /* DRAM configuration (DMC0 and DMC1) */
121 DMC1,
204 } else if (ch == DMC1) {
278 s5pv210_set_refresh(DMC1, 83000);
280 s5pv210_set_refresh(DMC1, 100000);
322 * 3. DMC1 refresh count for 133Mhz if (index == L4) is
327 s5pv210_set_refresh(DMC1, 133000);
433 * 10. DMC1 refresh counter
434 * L4 : DMC1 = 100Mhz 7.8us/(1/100) = 0x30c
435 * Others : DMC1 = 200Mhz 7.8us/(1/200) = 0x618
438 s5pv210_set_refresh(DMC1, 200000);
459 * DMC1 : 200Mhz
462 s5pv210_set_refresh(DMC1, 200000);
466 * DMC1 : 100Mhz
469 s5pv210_set_refresh(DMC1, 100000);