Lines Matching refs:s3c_freq
89 struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;
95 if (s3c_freq->is_dvs)
98 return clk_get_rate(s3c_freq->armclk) / 1000;
101 static int s3c2416_cpufreq_set_armdiv(struct s3c2416_data *s3c_freq,
106 if (clk_get_rate(s3c_freq->armdiv) / 1000 != freq) {
107 ret = clk_set_rate(s3c_freq->armdiv, freq * 1000);
118 static int s3c2416_cpufreq_enter_dvs(struct s3c2416_data *s3c_freq, int idx)
125 if (s3c_freq->is_dvs) {
131 clk_get_rate(s3c_freq->hclk) / 1000);
132 ret = clk_set_parent(s3c_freq->armclk, s3c_freq->hclk);
140 if (s3c_freq->vddarm) {
145 ret = regulator_set_voltage(s3c_freq->vddarm,
155 s3c_freq->is_dvs = 1;
160 static int s3c2416_cpufreq_leave_dvs(struct s3c2416_data *s3c_freq, int idx)
167 if (!s3c_freq->is_dvs) {
173 if (s3c_freq->vddarm) {
178 ret = regulator_set_voltage(s3c_freq->vddarm,
189 if (clk_get_rate(s3c_freq->armdiv) > clk_get_rate(s3c_freq->hclk)) {
191 clk_get_rate(s3c_freq->hclk) / 1000);
192 ret = s3c2416_cpufreq_set_armdiv(s3c_freq,
193 clk_get_rate(s3c_freq->hclk) / 1000);
196 clk_get_rate(s3c_freq->hclk) / 1000, ret);
202 clk_get_rate(s3c_freq->armdiv) / 1000);
204 ret = clk_set_parent(s3c_freq->armclk, s3c_freq->armdiv);
211 s3c_freq->is_dvs = 0;
219 struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;
225 idx = s3c_freq->freq_table[index].driver_data;
231 if (to_dvs && s3c_freq->disable_dvs) {
241 new_freq = (s3c_freq->is_dvs && !to_dvs)
242 ? clk_get_rate(s3c_freq->hclk) / 1000
243 : s3c_freq->freq_table[index].frequency;
247 ret = s3c2416_cpufreq_enter_dvs(s3c_freq, idx);
248 } else if (s3c_freq->is_dvs) {
250 ret = s3c2416_cpufreq_leave_dvs(s3c_freq, idx);
253 ret = s3c2416_cpufreq_set_armdiv(s3c_freq, new_freq);
263 static void s3c2416_cpufreq_cfg_regulator(struct s3c2416_data *s3c_freq)
269 count = regulator_count_voltages(s3c_freq->vddarm);
278 cpufreq_for_each_valid_entry(pos, s3c_freq->freq_table) {
284 v = regulator_list_voltage(s3c_freq->vddarm, i);
298 s3c_freq->regulator_latency = 1 * 1000 * 1000;
305 struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;
312 s3c_freq->disable_dvs = 1;
320 if (s3c_freq->is_dvs) {
345 struct s3c2416_data *s3c_freq = &s3c2416_cpufreq;
370 s3c_freq->freq_table = s3c2416_freq_table;
375 s3c_freq->freq_table = s3c2450_freq_table;
382 if (s3c_freq->freq_table == NULL) {
388 s3c_freq->is_dvs = 0;
390 s3c_freq->armdiv = clk_get(NULL, "armdiv");
391 if (IS_ERR(s3c_freq->armdiv)) {
392 ret = PTR_ERR(s3c_freq->armdiv);
397 s3c_freq->hclk = clk_get(NULL, "hclk");
398 if (IS_ERR(s3c_freq->hclk)) {
399 ret = PTR_ERR(s3c_freq->hclk);
407 rate = clk_get_rate(s3c_freq->hclk);
414 s3c_freq->armclk = clk_get(NULL, "armclk");
415 if (IS_ERR(s3c_freq->armclk)) {
416 ret = PTR_ERR(s3c_freq->armclk);
422 s3c_freq->vddarm = regulator_get(NULL, "vddarm");
423 if (IS_ERR(s3c_freq->vddarm)) {
424 ret = PTR_ERR(s3c_freq->vddarm);
429 s3c2416_cpufreq_cfg_regulator(s3c_freq);
431 s3c_freq->regulator_latency = 0;
434 cpufreq_for_each_entry(pos, s3c_freq->freq_table) {
437 if (!s3c_freq->hclk) {
447 rate = clk_round_rate(s3c_freq->armdiv,
460 cpufreq_generic_init(policy, s3c_freq->freq_table,
461 (500 * 1000) + s3c_freq->regulator_latency);
468 clk_put(s3c_freq->armclk);
471 clk_put(s3c_freq->hclk);
473 clk_put(s3c_freq->armdiv);