Lines Matching refs:base
38 void __iomem *base;
68 u32 tidr = readl_relaxed(t->base);
82 writel_relaxed(val, t->base + t->sysc);
90 writel_relaxed(DMTIMER_TYPE1_DISABLE, t->base + t->sysc);
95 void __iomem *syss = t->base + OMAP_TIMER_V1_SYS_STAT_OFFSET;
100 writel_relaxed(BIT(1) | BIT(2), t->base + t->ifctrl);
110 void __iomem *sysc = t->base + t->sysc;
373 t->base = of_iomap(np, 0);
374 if (!t->base)
418 pr_debug("dmtimer rev %08x sysc %08x\n", readl_relaxed(t->base),
419 readl_relaxed(t->base + t->sysc));
424 iounmap(t->base);
441 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat);
452 void __iomem *pend = t->base + t->pend;
456 writel_relaxed(0xffffffff - cycles, t->base + t->counter);
460 writel_relaxed(OMAP_TIMER_CTRL_ST, t->base + t->ctrl);
469 void __iomem *ctrl = t->base + t->ctrl;
481 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_stat);
490 void __iomem *pend = t->base + t->pend;
497 writel_relaxed(clkevt->period, t->base + t->load);
501 writel_relaxed(clkevt->period, t->base + t->counter);
506 t->base + t->ctrl);
531 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena);
532 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);
578 writel_relaxed(OMAP_TIMER_CTRL_POSTED, t->base + t->ifctrl);
585 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->irq_ena);
586 writel_relaxed(OMAP_TIMER_INT_OVERFLOW, t->base + t->wakeup);
595 iounmap(t->base);
719 return (u64)readl_relaxed(t->base + t->counter);
734 clksrc->loadval = readl_relaxed(t->base + t->counter);
750 writel_relaxed(clksrc->loadval, t->base + t->counter);
752 t->base + t->ctrl);
785 writel_relaxed(0, t->base + t->counter);
787 t->base + t->ctrl);
794 dmtimer_sched_clock_counter = t->base + t->counter;