Lines Matching defs:NPCM7XX_REG_TCSR0
22 #define NPCM7XX_REG_TCSR0 0x0 /* Timer 0 Control and Status Register */
61 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
63 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
73 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
75 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
85 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
88 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
100 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
103 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
115 val = readl(timer_of_base(to) + NPCM7XX_REG_TCSR0);
117 writel(val, timer_of_base(to) + NPCM7XX_REG_TCSR0);
158 timer_of_base(&npcm7xx_to) + NPCM7XX_REG_TCSR0);