Lines Matching refs:timer
51 * struct mchp_pit64b_timer - PIT64B timer data structure
66 * @timer: PIT64B timer
70 struct mchp_pit64b_timer timer;
78 /* Base address for clocksource timer. */
80 /* Default cycles for clockevent timer. */
93 * timer value whatever the lapse of time between the accesses.
103 static inline void mchp_pit64b_reset(struct mchp_pit64b_timer *timer,
111 writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
112 writel_relaxed(mode | timer->mode, timer->base + MCHP_PIT64B_MR);
113 writel_relaxed(high, timer->base + MCHP_PIT64B_MSB_PR);
114 writel_relaxed(low, timer->base + MCHP_PIT64B_LSB_PR);
115 writel_relaxed(irqs, timer->base + MCHP_PIT64B_IER);
116 writel_relaxed(MCHP_PIT64B_CR_START, timer->base + MCHP_PIT64B_CR);
131 struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
133 writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
140 struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
142 mchp_pit64b_reset(timer, mchp_pit64b_ce_cycles, MCHP_PIT64B_MR_CONT,
151 struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
153 mchp_pit64b_reset(timer, evt, MCHP_PIT64B_MR_ONE_SHOT,
161 struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
163 writel_relaxed(MCHP_PIT64B_CR_SWRST, timer->base + MCHP_PIT64B_CR);
164 if (timer->mode & MCHP_PIT64B_MR_SGCLK)
165 clk_disable_unprepare(timer->gclk);
166 clk_disable_unprepare(timer->pclk);
171 struct mchp_pit64b_timer *timer = to_mchp_pit64b_timer(cedev);
173 clk_prepare_enable(timer->pclk);
174 if (timer->mode & MCHP_PIT64B_MR_SGCLK)
175 clk_prepare_enable(timer->gclk);
183 readl_relaxed(irq_data->timer.base + MCHP_PIT64B_ISR);
210 * PIT64B timer may be fed by gclk or pclk. When gclk is used its rate has to
218 * then the function falls back on using PCLK as clock source for PIT64B timer
228 * | | | | MUX |--->| Divider |->|timer| |
240 static int __init mchp_pit64b_init_mode(struct mchp_pit64b_timer *timer,
247 pclk_rate = clk_get_rate(timer->pclk);
251 timer->mode = 0;
254 gclk_round = clk_round_rate(timer->gclk, max_rate);
266 timer->mode |= MCHP_PIT64B_MR_SGCLK;
267 clk_set_rate(timer->gclk, gclk_round);
281 timer->mode |= MCHP_PIT64B_MR_SGCLK;
282 clk_set_rate(timer->gclk, gclk_round);
286 timer->mode |= MCHP_PIT64B_PRES_TO_MODE(best_pres);
289 timer->mode & MCHP_PIT64B_MR_SGCLK ? "gclk" : "pclk", best_pres,
290 timer->mode & MCHP_PIT64B_MR_SGCLK ?
296 static int __init mchp_pit64b_init_clksrc(struct mchp_pit64b_timer *timer,
301 mchp_pit64b_reset(timer, ULLONG_MAX, MCHP_PIT64B_MR_CONT, 0);
303 mchp_pit64b_cs_base = timer->base;
305 ret = clocksource_mmio_init(timer->base, MCHP_PIT64B_NAME, clk_rate,
310 /* Stop timer. */
312 timer->base + MCHP_PIT64B_CR);
322 static int __init mchp_pit64b_init_clkevt(struct mchp_pit64b_timer *timer,
334 ce->timer.base = timer->base;
335 ce->timer.pclk = timer->pclk;
336 ce->timer.gclk = timer->gclk;
337 ce->timer.mode = timer->mode;
366 struct mchp_pit64b_timer timer;
372 timer.pclk = of_clk_get_by_name(node, "pclk");
373 if (IS_ERR(timer.pclk))
374 return PTR_ERR(timer.pclk);
376 timer.gclk = of_clk_get_by_name(node, "gclk");
377 if (IS_ERR(timer.gclk))
378 return PTR_ERR(timer.gclk);
380 timer.base = of_iomap(node, 0);
381 if (!timer.base)
393 ret = mchp_pit64b_init_mode(&timer, freq);
397 ret = clk_prepare_enable(timer.pclk);
401 if (timer.mode & MCHP_PIT64B_MR_SGCLK) {
402 ret = clk_prepare_enable(timer.gclk);
406 clk_rate = clk_get_rate(timer.gclk);
408 clk_rate = clk_get_rate(timer.pclk);
410 clk_rate = clk_rate / (MCHP_PIT64B_MODE_TO_PRES(timer.mode) + 1);
413 ret = mchp_pit64b_init_clkevt(&timer, clk_rate, irq);
415 ret = mchp_pit64b_init_clksrc(&timer, clk_rate);
423 if (timer.mode & MCHP_PIT64B_MR_SGCLK)
424 clk_disable_unprepare(timer.gclk);
426 clk_disable_unprepare(timer.pclk);
430 iounmap(timer.base);