Lines Matching refs:to
56 #define SYST_CON_REG(to) (timer_of_base(to) + SYST_CON)
57 #define SYST_VAL_REG(to) (timer_of_base(to) + SYST_VAL)
60 * SYST_CON_EN: Clock enable. Shall be set to
65 * SYST_CON_IRQ_EN: Set to allow interrupt.
67 * SYST_CON_IRQ_CLR: Set to clear interrupt.
75 static void mtk_syst_ack_irq(struct timer_of *to)
78 writel(SYST_CON_IRQ_CLR | SYST_CON_EN, SYST_CON_REG(to));
84 struct timer_of *to = to_timer_of(clkevt);
86 mtk_syst_ack_irq(to);
95 struct timer_of *to = to_timer_of(clkevt);
97 /* Enable clock to allow timeout tick update later */
98 writel(SYST_CON_EN, SYST_CON_REG(to));
104 writel(ticks, SYST_VAL_REG(to));
107 writel(SYST_CON_EN | SYST_CON_IRQ_EN, SYST_CON_REG(to));
135 static void mtk_gpt_clkevt_time_stop(struct timer_of *to, u8 timer)
139 val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
140 writel(val & ~GPT_CTRL_ENABLE, timer_of_base(to) +
144 static void mtk_gpt_clkevt_time_setup(struct timer_of *to,
147 writel(delay, timer_of_base(to) + GPT_CMP_REG(timer));
150 static void mtk_gpt_clkevt_time_start(struct timer_of *to,
156 writel(GPT_IRQ_ACK(timer), timer_of_base(to) + GPT_IRQ_ACK_REG);
158 val = readl(timer_of_base(to) + GPT_CTRL_REG(timer));
169 timer_of_base(to) + GPT_CTRL_REG(timer));
181 struct timer_of *to = to_timer_of(clk);
183 mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
184 mtk_gpt_clkevt_time_setup(to, to->of_clk.period, TIMER_CLK_EVT);
185 mtk_gpt_clkevt_time_start(to, true, TIMER_CLK_EVT);
193 struct timer_of *to = to_timer_of(clk);
195 mtk_gpt_clkevt_time_stop(to, TIMER_CLK_EVT);
196 mtk_gpt_clkevt_time_setup(to, event, TIMER_CLK_EVT);
197 mtk_gpt_clkevt_time_start(to, false, TIMER_CLK_EVT);
205 struct timer_of *to = to_timer_of(clkevt);
208 writel(GPT_IRQ_ACK(TIMER_CLK_EVT), timer_of_base(to) + GPT_IRQ_ACK_REG);
215 __init mtk_gpt_setup(struct timer_of *to, u8 timer, u8 option)
218 timer_of_base(to) + GPT_CTRL_REG(timer));
221 timer_of_base(to) + GPT_CLK_REG(timer));
223 writel(0x0, timer_of_base(to) + GPT_CMP_REG(timer));
226 timer_of_base(to) + GPT_CTRL_REG(timer));
229 static void mtk_gpt_enable_irq(struct timer_of *to, u8 timer)
234 writel(0x0, timer_of_base(to) + GPT_IRQ_EN_REG);
237 writel(0x3f, timer_of_base(to) + GPT_IRQ_ACK_REG);
239 val = readl(timer_of_base(to) + GPT_IRQ_EN_REG);
241 timer_of_base(to) + GPT_IRQ_EN_REG);
244 static struct timer_of to = {
262 to.clkevt.features = CLOCK_EVT_FEAT_DYNIRQ | CLOCK_EVT_FEAT_ONESHOT;
263 to.clkevt.set_state_shutdown = mtk_syst_clkevt_shutdown;
264 to.clkevt.set_state_oneshot = mtk_syst_clkevt_oneshot;
265 to.clkevt.tick_resume = mtk_syst_clkevt_resume;
266 to.clkevt.set_next_event = mtk_syst_clkevt_next_event;
267 to.of_irq.handler = mtk_syst_handler;
269 ret = timer_of_init(node, &to);
273 clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
283 to.clkevt.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT;
284 to.clkevt.set_state_shutdown = mtk_gpt_clkevt_shutdown;
285 to.clkevt.set_state_periodic = mtk_gpt_clkevt_set_periodic;
286 to.clkevt.set_state_oneshot = mtk_gpt_clkevt_shutdown;
287 to.clkevt.tick_resume = mtk_gpt_clkevt_shutdown;
288 to.clkevt.set_next_event = mtk_gpt_clkevt_next_event;
289 to.of_irq.handler = mtk_gpt_interrupt;
291 ret = timer_of_init(node, &to);
296 mtk_gpt_setup(&to, TIMER_CLK_SRC, GPT_CTRL_OP_FREERUN);
297 clocksource_mmio_init(timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC),
298 node->name, timer_of_rate(&to), 300, 32,
300 gpt_sched_reg = timer_of_base(&to) + GPT_CNT_REG(TIMER_CLK_SRC);
301 sched_clock_register(mtk_gpt_read_sched_clock, 32, timer_of_rate(&to));
304 mtk_gpt_setup(&to, TIMER_CLK_EVT, GPT_CTRL_OP_REPEAT);
305 clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
308 mtk_gpt_enable_irq(&to, TIMER_CLK_EVT);