Lines Matching defs:timer
7 * based on arch/mips/kernel/time.c timer driver
28 * The input frequency to the timer module for emulation is 2.5MHz which is
29 * common to all the timer channels (T1, T2, and T3). With a pre-scaler of 32,
32 * The input frequency to the timer module in silicon is configurable and
66 * struct ttc_timer - This definition defines local timer structure
68 * @base_addr: Base address of timer
104 * ttc_set_interval - Set the timer interval value
106 * @timer: Pointer to the timer instance
109 static void ttc_set_interval(struct ttc_timer *timer,
115 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
117 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
119 writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
127 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
131 * ttc_clock_event_interrupt - Clock event timer interrupt handler
141 struct ttc_timer *timer = &ttce->ttc;
144 readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
152 * __ttc_clocksource_read - Reads the timer counter register
154 * returns: Current timer counter register value
158 struct ttc_timer *timer = &to_ttc_timer_clksrc(cs)->ttc;
160 return (u64)readl_relaxed(timer->base_addr +
181 struct ttc_timer *timer = &ttce->ttc;
183 ttc_set_interval(timer, cycles);
188 * ttc_set_{shutdown|oneshot|periodic} - Sets the state of timer
195 struct ttc_timer *timer = &ttce->ttc;
198 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
200 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
207 struct ttc_timer *timer = &ttce->ttc;
209 ttc_set_interval(timer,
217 struct ttc_timer *timer = &ttce->ttc;
220 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
222 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
261 * store timer clock ctrl register so we can restore it in case
445 * Setup the clock event timer to be an interval timer which
477 struct device_node *timer = pdev->dev.of_node;
486 * and use it. Note that the event timer uses the interrupt and it's the
489 timer_baseaddr = devm_of_iomap(&pdev->dev, timer, 0, NULL);
491 pr_err("ERROR: invalid timer base address\n");
495 irq = irq_of_parse_and_map(timer, 1);
501 of_property_read_u32(timer, "timer-width", &timer_width);
505 clk_cs = of_clk_get(timer, clksel);
507 pr_err("ERROR: timer input clock not found\n");
513 clk_ce = of_clk_get(timer, clksel);
515 pr_err("ERROR: timer input clock not found\n");
528 pr_info("%pOFn #0 at %p, irq=%d\n", timer, timer_baseaddr, irq);