Lines Matching defs:base_addr
68 * @base_addr: Base address of timer
74 void __iomem *base_addr;
115 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
117 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
119 writel_relaxed(cycles, timer->base_addr + TTC_INTR_VAL_OFFSET);
127 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
144 readl_relaxed(timer->base_addr + TTC_ISR_OFFSET);
160 return (u64)readl_relaxed(timer->base_addr +
198 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
200 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
220 ctrl_reg = readl_relaxed(timer->base_addr + TTC_CNT_CNTRL_OFFSET);
222 writel_relaxed(ctrl_reg, timer->base_addr + TTC_CNT_CNTRL_OFFSET);
265 readl_relaxed(ttccs->ttc.base_addr +
291 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
301 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
311 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
349 ttccs->ttc.base_addr = base;
361 writel_relaxed(0x0, ttccs->ttc.base_addr + TTC_IER_OFFSET);
363 ttccs->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
365 ttccs->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
432 ttcce->ttc.base_addr = base;
449 writel_relaxed(0x23, ttcce->ttc.base_addr + TTC_CNT_CNTRL_OFFSET);
451 ttcce->ttc.base_addr + TTC_CLK_CNTRL_OFFSET);
452 writel_relaxed(0x1, ttcce->ttc.base_addr + TTC_IER_OFFSET);