Lines Matching refs:pwm
80 static struct samsung_pwm_clocksource pwm;
93 reg = readl(pwm.base + REG_TCFG0);
96 writel(reg, pwm.base + REG_TCFG0);
108 bits = (fls(divisor) - 1) - pwm.variant.div_base;
112 reg = readl(pwm.base + REG_TCFG1);
115 writel(reg, pwm.base + REG_TCFG1);
130 tcon = readl_relaxed(pwm.base + REG_TCON);
132 writel_relaxed(tcon, pwm.base + REG_TCON);
148 tcon = readl_relaxed(pwm.base + REG_TCON);
153 writel_relaxed(tcnt, pwm.base + REG_TCNTB(channel));
154 writel_relaxed(tcnt, pwm.base + REG_TCMPB(channel));
155 writel_relaxed(tcon, pwm.base + REG_TCON);
170 tcon = readl_relaxed(pwm.base + REG_TCON);
180 writel_relaxed(tcon, pwm.base + REG_TCON);
201 samsung_time_setup(pwm.event_id, cycles);
202 samsung_time_start(pwm.event_id, false);
209 samsung_time_stop(pwm.event_id);
215 samsung_time_stop(pwm.event_id);
216 samsung_time_setup(pwm.event_id, pwm.clock_count_per_tick - 1);
217 samsung_time_start(pwm.event_id, true);
223 samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
224 samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
226 if (pwm.variant.has_tint_cstat) {
227 u32 mask = (1 << pwm.event_id);
228 writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
249 if (pwm.variant.has_tint_cstat) {
250 u32 mask = (1 << pwm.event_id);
251 writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
265 pclk = clk_get_rate(pwm.timerclk);
267 samsung_timer_set_prescale(pwm.event_id, pwm.tscaler_div);
268 samsung_timer_set_divisor(pwm.event_id, pwm.tdiv);
270 clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
271 pwm.clock_count_per_tick = clock_rate / HZ;
275 clock_rate, 1, pwm.tcnt_max);
277 irq_number = pwm.irq[pwm.event_id];
283 if (pwm.variant.has_tint_cstat) {
284 u32 mask = (1 << pwm.event_id);
285 writel(mask | (mask << 5), pwm.base + REG_TINT_CSTAT);
291 samsung_time_stop(pwm.source_id);
296 samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
297 samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
299 samsung_time_setup(pwm.source_id, pwm.tcnt_max);
300 samsung_time_start(pwm.source_id, true);
305 return ~readl_relaxed(pwm.source_reg);
334 pclk = clk_get_rate(pwm.timerclk);
336 samsung_timer_set_prescale(pwm.source_id, pwm.tscaler_div);
337 samsung_timer_set_divisor(pwm.source_id, pwm.tdiv);
339 clock_rate = pclk / (pwm.tscaler_div * pwm.tdiv);
341 samsung_time_setup(pwm.source_id, pwm.tcnt_max);
342 samsung_time_start(pwm.source_id, true);
344 if (pwm.source_id == 4)
345 pwm.source_reg = pwm.base + 0x40;
347 pwm.source_reg = pwm.base + pwm.source_id * 0x0c + 0x14;
350 pwm.variant.bits, clock_rate);
352 samsung_clocksource.mask = CLOCKSOURCE_MASK(pwm.variant.bits);
358 clk_prepare_enable(pwm.timerclk);
360 pwm.tcnt_max = (1UL << pwm.variant.bits) - 1;
361 if (pwm.variant.bits == 16) {
362 pwm.tscaler_div = 25;
363 pwm.tdiv = 2;
365 pwm.tscaler_div = 2;
366 pwm.tdiv = 1;
378 mask = ~pwm.variant.output_mask & ((1 << SAMSUNG_PWM_NUM) - 1);
384 pwm.source_id = channel;
392 pwm.event_id = channel;
403 pwm.base = base;
404 memcpy(&pwm.variant, variant, sizeof(pwm.variant));
405 memcpy(pwm.irq, irqs, SAMSUNG_PWM_NUM * sizeof(*irqs));
407 pwm.timerclk = clk_get(NULL, "timers");
408 if (IS_ERR(pwm.timerclk))
423 memcpy(&pwm.variant, variant, sizeof(pwm.variant));
425 pwm.irq[i] = irq_of_parse_and_map(np, i);
427 of_property_for_each_u32(np, "samsung,pwm-outputs", prop, cur, val) {
429 pr_warn("%s: invalid channel index in samsung,pwm-outputs property\n", __func__);
432 pwm.variant.output_mask |= 1 << val;
435 pwm.base = of_iomap(np, 0);
436 if (!pwm.base) {
441 pwm.timerclk = of_clk_get_by_name(np, "timers");
442 if (IS_ERR(pwm.timerclk)) {
444 return PTR_ERR(pwm.timerclk);
461 TIMER_OF_DECLARE(s3c2410_pwm, "samsung,s3c2410-pwm", s3c2410_pwm_clocksource_init);
474 TIMER_OF_DECLARE(s3c6400_pwm, "samsung,s3c6400-pwm", s3c64xx_pwm_clocksource_init);
487 TIMER_OF_DECLARE(s5p6440_pwm, "samsung,s5p6440-pwm", s5p64x0_pwm_clocksource_init);
500 TIMER_OF_DECLARE(s5pc100_pwm, "samsung,s5pc100-pwm", s5p_pwm_clocksource_init);