Lines Matching defs:base
105 void __iomem *base;
113 writel_relaxed(delta, priv.base + HW_MR0);
115 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG);
122 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + CLR_REG);
137 priv.base + HW_MCR + SET_REG);
147 priv.base + HW_MCR + CLR_REG);
149 writel_relaxed(priv.ticks_per_jiffy, priv.base + HW_MR0);
151 writel_relaxed(BM_C0_EN, priv.base + HW_TCR + SET_REG);
173 writel_relaxed(BM_IR_MR0, priv.base + HW_IR);
190 priv.base = of_io_request_and_map(np, 0, np->name);
191 if (IS_ERR(priv.base)) {
193 return PTR_ERR(priv.base);
217 writel_relaxed(BM_DIR_DEFAULT, priv.base + HW_DIR);
219 writel_relaxed(BM_PR_DISABLE, priv.base + HW_PR);
221 writel_relaxed(BM_CTCR_DEFAULT, priv.base + HW_CTCR);
223 writel_relaxed(BM_MCR_INT_EN(0) , priv.base + HW_MCR);
226 clocksource_mmio_init(priv.base + HW_TC1, DRIVER_NAME, rate,
231 writel_relaxed(0xffffffff, priv.base + HW_MR1);
233 writel_relaxed(BM_C1_EN, priv.base + HW_TCR + SET_REG);