Lines Matching defs:rate
21 * rate - rate is adjustable. clk->rate = ceiling(parent->rate / divisor)
49 unsigned long rate, u16 flags)
55 up = DIV_ROUND_UP_ULL((u64)parent_rate, rate);
56 down = DIV_ROUND_DOWN_ULL((u64)parent_rate, rate);
64 return (rate - up_rate) <= (down_rate - rate) ? up : down;
67 return DIV_ROUND_CLOSEST(parent_rate, rate);
72 * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
74 * @parent_rate: rate of parent clock
113 * zynqmp_clk_divider_round_rate() - Round rate of divider clock
115 * @rate: rate of clock to be set
116 * @prate: rate of parent clock
121 unsigned long rate,
152 rate = divider_round_rate(hw, rate, prate, NULL, width, divider->flags);
154 if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (rate % *prate))
155 *prate = rate;
157 return rate;
161 * zynqmp_clk_divider_set_rate() - Set rate of divider clock
163 * @rate: rate of clock to be set
164 * @parent_rate: rate of parent clock
168 static int zynqmp_clk_divider_set_rate(struct clk_hw *hw, unsigned long rate,
178 value = zynqmp_divider_get_val(parent_rate, rate, divider->flags);
275 * To achieve best possible rate, maximum limit of divider is required