Lines Matching defs:divider
7 * Adjustable divider clock implementation
16 * DOC: basic adjustable divider clock that cannot gate
32 * struct zynqmp_clk_divider - adjustable divider clock
35 * @is_frac: The divider is a fractional divider
72 * zynqmp_clk_divider_recalc_rate() - Recalc rate of divider clock
81 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
83 u32 clk_id = divider->clk_id;
84 u32 div_type = divider->div_type;
91 pr_warn_once("%s() get divider failed for %s, ret = %d\n",
99 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
103 WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
113 * zynqmp_clk_divider_round_rate() - Round rate of divider clock
124 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
126 u32 clk_id = divider->clk_id;
127 u32 div_type = divider->div_type;
133 if (divider->flags & CLK_DIVIDER_READ_ONLY) {
137 pr_warn_once("%s() get divider failed for %s, ret = %d\n",
144 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
150 width = fls(divider->max_div);
152 rate = divider_round_rate(hw, rate, prate, NULL, width, divider->flags);
154 if (divider->is_frac && (clk_hw_get_flags(hw) & CLK_SET_RATE_PARENT) && (rate % *prate))
161 * zynqmp_clk_divider_set_rate() - Set rate of divider clock
171 struct zynqmp_clk_divider *divider = to_zynqmp_clk_divider(hw);
173 u32 clk_id = divider->clk_id;
174 u32 div_type = divider->div_type;
178 value = zynqmp_divider_get_val(parent_rate, rate, divider->flags);
187 if (divider->flags & CLK_DIVIDER_POWER_OF_TWO)
193 pr_warn_once("%s() set divider failed for %s, ret = %d\n",
234 * zynqmp_clk_register_divider() - Register a divider clock
241 * Return: clock hardware to registered clock divider
254 /* allocate the divider */
275 * To achieve best possible rate, maximum limit of divider is required