Lines Matching defs:clock
3 * Zynq UltraScale+ MPSoC clock controller
50 * @id: Parent clock ID
62 * @valid: Validity flag of clock
66 * @parent: Parent of clock
67 * @num_parents: Number of parents of clock
135 static struct zynqmp_clock *clock;
140 * zynqmp_is_valid_clock() - Check whether clock is valid or not
143 * Return: 1 if clock is valid, 0 if clock is invalid else error code
150 return clock[clk_id].valid;
154 * zynqmp_get_clock_name() - Get name of clock from Clock index
156 * @clk_name: Name of clock
166 strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN);
174 * zynqmp_get_clock_type() - Get type of clock
186 *type = clock[clk_id].type;
216 * zynqmp_pm_clock_get_name() - Get the name of clock for given id
217 * @clock_id: ID of the clock to be queried
218 * @response: Name of the clock with the given id
220 * This function is used to get name of clock specified by given
221 * clock ID.
241 * zynqmp_pm_clock_get_topology() - Get the topology of clock for given id
242 * @clock_id: ID of the clock to be queried
243 * @index: Node index of clock topology
246 * This function is used to get topology information for the clock
247 * specified by given clock ID.
276 * clock framework
277 * @name: Name of this clock
279 * @parents: Name of this clock's parents
283 * Return: clock hardware to the registered clock
315 * zynqmp_pm_clock_get_parents() - Get the first 3 parents of clock for given id
318 * @response: Parents of the given clock
320 * This function is used to get 3 parents for the clock specified by
321 * given clock ID.
349 * zynqmp_pm_clock_get_attributes() - Get the attributes of clock for given id
353 * This function is used to get clock's attributes(e.g. valid, clock type, etc).
374 * __zynqmp_clock_get_topology() - Get topology data of clock from firmware
409 * zynqmp_clock_get_topology() - Get topology of clock from firmware using
426 ret = zynqmp_pm_clock_get_topology(clock[clk_id].clk_id, j,
440 * __zynqmp_clock_get_parents() - Get parents info of clock from firmware
493 ret = zynqmp_pm_clock_get_parents(clock[clk_id].clk_id, j,
521 u32 total_parents = clock[clk_id].num_parents;
525 clk_nodes = clock[clk_id].node;
526 parents = clock[clk_id].parent;
532 ret = of_property_match_string(np, "clock-names",
550 * zynqmp_register_clk_topology() - Register clock topology
556 * Return: Returns either clock hardware or error+reason
568 nodes = clock[clk_id].node;
569 num_nodes = clock[clk_id].num_nodes;
570 clk_dev_id = clock[clk_id].clk_id;
574 * Clock name received from firmware is output clock name.
575 * Intermediate clock names are postfixed with type of clock.
620 /* get clock name, continue to next clock if name not found */
624 /* Check if clock is valid and output clock.
625 * Do not register invalid or external clock.
631 /* Get parents of clock*/
635 clock[i].clk_name);
648 clock[i].clk_name, PTR_ERR(zynqmp_data->hws[i]));
656 * zynqmp_get_clock_info() - Get clock information from firmware using PM_API
671 clock[i].valid = FIELD_GET(CLK_ATTR_VALID, attr.attr[0]);
672 /* skip query for Invalid clock */
677 clock[i].type = FIELD_GET(CLK_ATTR_TYPE, attr.attr[0]) ?
684 clock[i].clk_id = FIELD_PREP(CLK_ATTR_NODE_CLASS, class) |
689 zynqmp_pm_clock_get_name(clock[i].clk_id, &name);
699 strncpy(clock[i].clk_name, name.name, MAX_NAME_LEN);
702 /* Get topology of all clock */
708 ret = zynqmp_clock_get_topology(i, clock[i].node,
709 &clock[i].num_nodes);
713 ret = zynqmp_clock_get_parents(i, clock[i].parent,
714 &clock[i].num_parents);
721 * zynqmp_clk_setup() - Setup the clock framework and register clocks
739 clock = kcalloc(clock_max_idx, sizeof(*clock), GFP_KERNEL);
740 if (!clock) {