Lines Matching refs:_parent
37 #define ZX_PLL(_name, _parent, _reg, _table, _pd, _lock) \
44 .hw.init = CLK_HW_INIT(_name, _parent, &zx_pll_ops, \
52 #define ZX296718_PLL(_name, _parent, _reg, _table) \
53 ZX_PLL(_name, _parent, _reg, _table, 0xff, 30)
60 #define GATE(_id, _name, _parent, _reg, _bit, _flag, _gflags) \
68 _parent, \
80 #define FFACTOR(_id, _name, _parent, _mult, _div, _flag) \
86 _parent, \
98 #define MUX_F(_id, _name, _parent, _reg, _shift, _width, _flag, _mflag) \
107 _parent, \
114 #define MUX(_id, _name, _parent, _reg, _shift, _width) \
115 MUX_F(_id, _name, _parent, _reg, _shift, _width, 0, 0)
122 #define DIV_T(_id, _name, _parent, _reg, _shift, _width, _flag, _table) \
132 _parent, \
147 #define AUDIO_DIV(_id, _name, _parent, _reg) \
152 _parent, \