Lines Matching defs:reg_base
47 hw_cfg0 = readl_relaxed(zx_pll->reg_base);
48 hw_cfg1 = readl_relaxed(zx_pll->reg_base + CFG0_CFG1_OFFSET);
100 writel_relaxed(config->cfg0, zx_pll->reg_base);
101 writel_relaxed(config->cfg1, zx_pll->reg_base + CFG0_CFG1_OFFSET);
115 reg = readl_relaxed(zx_pll->reg_base);
116 writel_relaxed(reg & ~BIT(zx_pll->pd_bit), zx_pll->reg_base);
118 return readl_relaxed_poll_timeout(zx_pll->reg_base, reg,
130 reg = readl_relaxed(zx_pll->reg_base);
131 writel_relaxed(reg | BIT(zx_pll->pd_bit), zx_pll->reg_base);
139 reg = readl_relaxed(zx_pll->reg_base);
155 unsigned long flags, void __iomem *reg_base,
173 zx_pll->reg_base = reg_base;
237 reg = readl_relaxed(zx_audio->reg_base);
260 writel_relaxed(reg, zx_audio->reg_base);
271 reg = readl_relaxed(zx_audio->reg_base);
272 writel_relaxed(reg & ~ZX_AUDIO_EN, zx_audio->reg_base);
281 reg = readl_relaxed(zx_audio->reg_base);
282 writel_relaxed(reg | ZX_AUDIO_EN, zx_audio->reg_base);
296 void __iomem *reg_base)
312 zx_audio->reg_base = reg_base;
398 reg_frac = readl_relaxed(zx_audio_div->reg_base);
399 reg_int = readl_relaxed(zx_audio_div->reg_base + 0x4);
426 writel_relaxed(divt.frac_reg, zx_audio_div->reg_base);
428 val = readl_relaxed(zx_audio_div->reg_base + 0x4);
431 writel_relaxed(val, zx_audio_div->reg_base + 0x4);
435 val = readl_relaxed(zx_audio_div->reg_base + 0x4);
437 writel_relaxed(val, zx_audio_div->reg_base + 0x4);