Lines Matching refs:zx_gate
218 static inline struct clk *zx_gate(const char *name, const char *parent,
387 zx_gate("a9_as0_aclk", "matrix_aclk", CLK_EN0, 0);
389 zx_gate("a9_as1_aclk", "a9_as1_aclk_div", CLK_EN0, 1);
391 zx_gate("a9_trace_clkin", "a9_trace_clkin_mux", CLK_EN0, 2);
393 zx_gate("decppu_axi_m_aclk", "decppu_aclk_mux", CLK_EN0, 3);
395 zx_gate("decppu_ahb_s_hclk", "main_hclk", CLK_EN0, 4);
397 zx_gate("ppu_axi_m_aclk", "ppu_aclk_mux", CLK_EN0, 5);
399 zx_gate("ppu_ahb_s_hclk", "main_hclk", CLK_EN0, 6);
401 zx_gate("vou_axi_m_aclk", "vou_aclk_mux", CLK_EN0, 7);
403 zx_gate("vou_apb_pclk", "main_pclk", CLK_EN0, 8);
405 zx_gate("vou_main_channel_wclk", "vou_main_wclk_mux",
408 zx_gate("vou_aux_channel_wclk", "vou_aux_wclk_mux",
411 zx_gate("vou_hdmi_osclk_cec", "clk_2", CLK_EN0, 11);
413 zx_gate("vou_scaler_wclk", "vou_scaler_wclk_mux", CLK_EN0, 12);
415 zx_gate("mali400_axi_m_aclk", "mali400_aclk_mux", CLK_EN0, 13);
417 zx_gate("mali400_apb_pclk", "main_pclk", CLK_EN0, 14);
419 zx_gate("r2d_wclk", "r2d_wclk_mux", CLK_EN0, 15);
421 zx_gate("r2d_axi_m_aclk", "r2d_aclk_mux", CLK_EN0, 16);
423 zx_gate("r2d_ahb_hclk", "main_hclk", CLK_EN0, 17);
425 zx_gate("ddr3_axi_s0_aclk", "matrix_aclk", CLK_EN0, 18);
427 zx_gate("ddr3_apb_pclk", "main_pclk", CLK_EN0, 19);
429 zx_gate("ddr3_wclk", "ddr_wclk_mux", CLK_EN0, 20);
431 zx_gate("usb20_0_ahb_hclk", "main_hclk", CLK_EN0, 21);
433 zx_gate("usb20_0_extrefclk", "clk_12", CLK_EN0, 22);
435 zx_gate("usb20_1_ahb_hclk", "main_hclk", CLK_EN0, 23);
437 zx_gate("usb20_1_extrefclk", "clk_12", CLK_EN0, 24);
439 zx_gate("usb20_2_ahb_hclk", "main_hclk", CLK_EN0, 25);
441 zx_gate("usb20_2_extrefclk", "clk_12", CLK_EN0, 26);
443 zx_gate("gmac_axi_m_aclk", "matrix_aclk", CLK_EN0, 27);
445 zx_gate("gmac_apb_pclk", "main_pclk", CLK_EN0, 28);
447 zx_gate("gmac_125_clkin", "clk_125", CLK_EN0, 29);
449 zx_gate("gmac_rmii_clkin", "clk_50", CLK_EN0, 30);
451 zx_gate("gmac_25M_clk", "clk_25", CLK_EN0, 31);
453 zx_gate("nandflash_ahb_hclk", "main_hclk", CLK_EN1, 0);
455 zx_gate("nandflash_wclk", "nand_wclk_mux", CLK_EN1, 1);
457 zx_gate("lsp0_apb_pclk", "main_pclk", CLK_EN1, 2);
459 zx_gate("lsp0_ahb_hclk", "main_hclk", CLK_EN1, 3);
461 zx_gate("lsp0_26M_wclk", "lsp_26_wclk_mux", CLK_EN1, 4);
463 zx_gate("lsp0_104M_wclk", "pll_lsp_104M", CLK_EN1, 5);
465 zx_gate("lsp0_16M384_wclk", "clk_16M384", CLK_EN1, 6);
467 zx_gate("lsp1_apb_pclk", "main_pclk", CLK_EN1, 7);
471 zx_gate("lsp1_26M_wclk", "lsp_26_wclk_mux", CLK_EN1, 31);
473 zx_gate("lsp1_104M_wclk", "pll_lsp_104M", CLK_EN1, 9);
475 zx_gate("lsp1_32K_clk", "clk_32K768", CLK_EN1, 10);
477 zx_gate("aon_hclk", "main_hclk", CLK_EN1, 11);
479 zx_gate("sys_ctrl_pclk", "main_pclk", CLK_EN1, 12);
481 zx_gate("dma_pclk", "main_pclk", CLK_EN1, 13);
483 zx_gate("dma_aclk", "matrix_aclk", CLK_EN1, 14);
485 zx_gate("sec_hclk", "main_hclk", CLK_EN1, 15);
487 zx_gate("aes_wclk", "sec_wclk_div", CLK_EN1, 16);
489 zx_gate("des_wclk", "sec_wclk_div", CLK_EN1, 17);
491 zx_gate("iram_aclk", "matrix_aclk", CLK_EN1, 18);
493 zx_gate("irom_aclk", "matrix_aclk", CLK_EN1, 19);
495 zx_gate("boot_ctrl_hclk", "main_hclk", CLK_EN1, 20);
497 zx_gate("efuse_clk_30", "osc", CLK_EN1, 21);
543 zx_gate("vl0_clk", "vl0_mux", VOU_LOCAL_CLKEN, 8);
545 zx_gate("vl1_clk", "vl1_mux", VOU_LOCAL_CLKEN, 9);
547 zx_gate("vl2_clk", "vl2_mux", VOU_LOCAL_CLKEN, 10);
549 zx_gate("gl0_clk", "gl0_mux", VOU_LOCAL_CLKEN, 5);
551 zx_gate("gl1_clk", "gl1_mux", VOU_LOCAL_CLKEN, 6);
553 zx_gate("gl2_clk", "gl2_mux", VOU_LOCAL_CLKEN, 7);
555 zx_gate("wb_clk", "wb_mux", VOU_LOCAL_CLKEN, 11);
557 zx_gate("cl_clk", "vou_main_channel_div", VOU_LOCAL_CLKEN, 12);
559 zx_gate("main_mix_clk", "vou_main_channel_div",
562 zx_gate("aux_mix_clk", "vou_aux_channel_div",
565 zx_gate("hdmi_clk", "hdmi_mux", VOU_LOCAL_CLKEN, 2);
567 zx_gate("vou_tv_enc_hd_dac_clk", "vou_tv_enc_hd_div",
570 zx_gate("vou_tv_enc_sd_dac_clk", "vou_tv_enc_sd_div",
608 zx_gate("sdmmc1_wclk", "sdmmc1_wclk_div", CLK_SDMMC1, 1);
610 zx_gate("sdmmc1_pclk", "lsp0_apb_pclk", CLK_SDMMC1, 0);
613 zx_gate("gpio_clk", "lsp0_apb_pclk", CLK_GPIO, 0);
620 zx_gate("spdif0_wclk", "spdif0_wclk_mux", CLK_SPDIF0, 1);
622 zx_gate("spdif0_pclk", "lsp0_apb_pclk", CLK_SPDIF0, 0);
633 zx_gate("i2s0_wclk", "i2s0_wclk_mux", CLK_I2S0, 1);
635 zx_gate("i2s0_pclk", "lsp0_apb_pclk", CLK_I2S0, 0);
644 zx_gate("i2s1_wclk", "i2s1_wclk_mux", CLK_I2S1, 1);
646 zx_gate("i2s1_pclk", "lsp0_apb_pclk", CLK_I2S1, 0);
655 zx_gate("i2s2_wclk", "i2s2_wclk_mux", CLK_I2S2, 1);
657 zx_gate("i2s2_pclk", "lsp0_apb_pclk", CLK_I2S2, 0);
692 zx_gate("uart0_wclk", "uart0_wclk_mux", CLK_UART0, 31);
694 zx_gate("uart0_pclk", "lsp1_apb_pclk", CLK_UART0, 0);
701 zx_gate("uart1_wclk", "uart1_wclk_mux", CLK_UART1, 1);
703 zx_gate("uart1_pclk", "lsp1_apb_pclk", CLK_UART1, 0);
712 zx_gate("sdmmc0_wclk", "sdmmc0_wclk_div", CLK_SDMMC0, 1);
714 zx_gate("sdmmc0_pclk", "lsp1_apb_pclk", CLK_SDMMC0, 0);
720 zx_gate("spdif1_wclk", "spdif1_wclk_mux", CLK_SPDIF1, 1);
722 zx_gate("spdif1_pclk", "lsp1_apb_pclk", CLK_SPDIF1, 0);