Lines Matching refs:clk
7 #include <linux/clk-provider.h>
10 #include "clk.h"
18 static struct clk *topclk[ZX296702_TOPCLK_END];
19 static struct clk *lsp0clk[ZX296702_LSP0CLK_END];
20 static struct clk *lsp1clk[ZX296702_LSP1CLK_END];
196 static inline struct clk *zx_divtbl(const char *name, const char *parent,
204 static inline struct clk *zx_div(const char *name, const char *parent,
211 static inline struct clk *zx_mux(const char *name, const char * const *parents,
218 static inline struct clk *zx_gate(const char *name, const char *parent,
227 struct clk **clk = topclk;
233 clk[ZX296702_OSC] =
235 clk[ZX296702_PLL_A9] =
241 clk[ZX296702_PLL_A9_350M] =
244 clk[ZX296702_PLL_MAC_1000M] =
247 clk[ZX296702_PLL_MAC_333M] =
250 clk[ZX296702_PLL_MM0_1188M] =
253 clk[ZX296702_PLL_MM0_396M] =
256 clk[ZX296702_PLL_MM0_198M] =
259 clk[ZX296702_PLL_MM1_108M] =
262 clk[ZX296702_PLL_MM1_72M] =
265 clk[ZX296702_PLL_MM1_54M] =
268 clk[ZX296702_PLL_LSP_104M] =
271 clk[ZX296702_PLL_LSP_26M] =
274 clk[ZX296702_PLL_DDR_266M] =
277 clk[ZX296702_PLL_AUDIO_294M912] =
282 clk[ZX296702_MATRIX_ACLK] =
285 clk[ZX296702_MAIN_HCLK] =
288 clk[ZX296702_MAIN_PCLK] =
293 clk[ZX296702_CLK_500] =
296 clk[ZX296702_CLK_250] =
299 clk[ZX296702_CLK_125] =
301 clk[ZX296702_CLK_148M5] =
304 clk[ZX296702_CLK_74M25] =
307 clk[ZX296702_A9_WCLK] =
310 clk[ZX296702_A9_AS1_ACLK_MUX] =
313 clk[ZX296702_A9_TRACE_CLKIN_MUX] =
316 clk[ZX296702_A9_AS1_ACLK_DIV] =
321 clk[ZX296702_CLK_2] =
324 clk[ZX296702_CLK_27] =
327 clk[ZX296702_DECPPU_ACLK_MUX] =
330 clk[ZX296702_PPU_ACLK_MUX] =
333 clk[ZX296702_MALI400_ACLK_MUX] =
336 clk[ZX296702_VOU_ACLK_MUX] =
339 clk[ZX296702_VOU_MAIN_WCLK_MUX] =
342 clk[ZX296702_VOU_AUX_WCLK_MUX] =
345 clk[ZX296702_VOU_SCALER_WCLK_MUX] =
349 clk[ZX296702_R2D_ACLK_MUX] =
352 clk[ZX296702_R2D_WCLK_MUX] =
357 clk[ZX296702_CLK_50] =
360 clk[ZX296702_CLK_25] =
363 clk[ZX296702_CLK_12] =
366 clk[ZX296702_CLK_16M384] =
369 clk[ZX296702_CLK_32K768] =
372 clk[ZX296702_SEC_WCLK_DIV] =
375 clk[ZX296702_DDR_WCLK_MUX] =
378 clk[ZX296702_NAND_WCLK_MUX] =
381 clk[ZX296702_LSP_26_WCLK_MUX] =
386 clk[ZX296702_A9_AS0_ACLK] =
388 clk[ZX296702_A9_AS1_ACLK] =
390 clk[ZX296702_A9_TRACE_CLKIN] =
392 clk[ZX296702_DECPPU_AXI_M_ACLK] =
394 clk[ZX296702_DECPPU_AHB_S_HCLK] =
396 clk[ZX296702_PPU_AXI_M_ACLK] =
398 clk[ZX296702_PPU_AHB_S_HCLK] =
400 clk[ZX296702_VOU_AXI_M_ACLK] =
402 clk[ZX296702_VOU_APB_PCLK] =
404 clk[ZX296702_VOU_MAIN_CHANNEL_WCLK] =
407 clk[ZX296702_VOU_AUX_CHANNEL_WCLK] =
410 clk[ZX296702_VOU_HDMI_OSCLK_CEC] =
412 clk[ZX296702_VOU_SCALER_WCLK] =
414 clk[ZX296702_MALI400_AXI_M_ACLK] =
416 clk[ZX296702_MALI400_APB_PCLK] =
418 clk[ZX296702_R2D_WCLK] =
420 clk[ZX296702_R2D_AXI_M_ACLK] =
422 clk[ZX296702_R2D_AHB_HCLK] =
424 clk[ZX296702_DDR3_AXI_S0_ACLK] =
426 clk[ZX296702_DDR3_APB_PCLK] =
428 clk[ZX296702_DDR3_WCLK] =
430 clk[ZX296702_USB20_0_AHB_HCLK] =
432 clk[ZX296702_USB20_0_EXTREFCLK] =
434 clk[ZX296702_USB20_1_AHB_HCLK] =
436 clk[ZX296702_USB20_1_EXTREFCLK] =
438 clk[ZX296702_USB20_2_AHB_HCLK] =
440 clk[ZX296702_USB20_2_EXTREFCLK] =
442 clk[ZX296702_GMAC_AXI_M_ACLK] =
444 clk[ZX296702_GMAC_APB_PCLK] =
446 clk[ZX296702_GMAC_125_CLKIN] =
448 clk[ZX296702_GMAC_RMII_CLKIN] =
450 clk[ZX296702_GMAC_25M_CLK] =
452 clk[ZX296702_NANDFLASH_AHB_HCLK] =
454 clk[ZX296702_NANDFLASH_WCLK] =
456 clk[ZX296702_LSP0_APB_PCLK] =
458 clk[ZX296702_LSP0_AHB_HCLK] =
460 clk[ZX296702_LSP0_26M_WCLK] =
462 clk[ZX296702_LSP0_104M_WCLK] =
464 clk[ZX296702_LSP0_16M384_WCLK] =
466 clk[ZX296702_LSP1_APB_PCLK] =
469 * UART does not work after parent clk is disabled/enabled */
470 clk[ZX296702_LSP1_26M_WCLK] =
472 clk[ZX296702_LSP1_104M_WCLK] =
474 clk[ZX296702_LSP1_32K_CLK] =
476 clk[ZX296702_AON_HCLK] =
478 clk[ZX296702_SYS_CTRL_PCLK] =
480 clk[ZX296702_DMA_PCLK] =
482 clk[ZX296702_DMA_ACLK] =
484 clk[ZX296702_SEC_HCLK] =
486 clk[ZX296702_AES_WCLK] =
488 clk[ZX296702_DES_WCLK] =
490 clk[ZX296702_IRAM_ACLK] =
492 clk[ZX296702_IROM_ACLK] =
494 clk[ZX296702_BOOT_CTRL_HCLK] =
496 clk[ZX296702_EFUSE_CLK_30] =
500 clk[ZX296702_VOU_MAIN_CHANNEL_DIV] =
503 clk[ZX296702_VOU_AUX_CHANNEL_DIV] =
506 clk[ZX296702_VOU_TV_ENC_HD_DIV] =
509 clk[ZX296702_VOU_TV_ENC_SD_DIV] =
512 clk[ZX296702_VL0_MUX] =
515 clk[ZX296702_VL1_MUX] =
518 clk[ZX296702_VL2_MUX] =
521 clk[ZX296702_GL0_MUX] =
524 clk[ZX296702_GL1_MUX] =
527 clk[ZX296702_GL2_MUX] =
530 clk[ZX296702_WB_MUX] =
533 clk[ZX296702_HDMI_MUX] =
536 clk[ZX296702_VOU_TV_ENC_HD_MUX] =
539 clk[ZX296702_VOU_TV_ENC_SD_MUX] =
542 clk[ZX296702_VL0_CLK] =
544 clk[ZX296702_VL1_CLK] =
546 clk[ZX296702_VL2_CLK] =
548 clk[ZX296702_GL0_CLK] =
550 clk[ZX296702_GL1_CLK] =
552 clk[ZX296702_GL2_CLK] =
554 clk[ZX296702_WB_CLK] =
556 clk[ZX296702_CL_CLK] =
558 clk[ZX296702_MAIN_MIX_CLK] =
561 clk[ZX296702_AUX_MIX_CLK] =
564 clk[ZX296702_HDMI_CLK] =
566 clk[ZX296702_VOU_TV_ENC_HD_DAC_CLK] =
569 clk[ZX296702_VOU_TV_ENC_SD_DAC_CLK] =
574 clk[ZX296702_A9_PERIPHCLK] =
579 if (IS_ERR(clk[i])) {
580 pr_err("zx296702 clk %d: register failed with %ld\n",
581 i, PTR_ERR(clk[i]));
590 CLK_OF_DECLARE(zx296702_top_clk, "zte,zx296702-topcrm-clk",
595 struct clk **clk = lsp0clk;
602 clk[ZX296702_SDMMC1_WCLK_MUX] =
605 clk[ZX296702_SDMMC1_WCLK_DIV] =
607 clk[ZX296702_SDMMC1_WCLK] =
609 clk[ZX296702_SDMMC1_PCLK] =
612 clk[ZX296702_GPIO_CLK] =
616 clk[ZX296702_SPDIF0_WCLK_MUX] =
619 clk[ZX296702_SPDIF0_WCLK] =
621 clk[ZX296702_SPDIF0_PCLK] =
624 clk[ZX296702_SPDIF0_DIV] =
629 clk[ZX296702_I2S0_WCLK_MUX] =
632 clk[ZX296702_I2S0_WCLK] =
634 clk[ZX296702_I2S0_PCLK] =
637 clk[ZX296702_I2S0_DIV] =
640 clk[ZX296702_I2S1_WCLK_MUX] =
643 clk[ZX296702_I2S1_WCLK] =
645 clk[ZX296702_I2S1_PCLK] =
648 clk[ZX296702_I2S1_DIV] =
651 clk[ZX296702_I2S2_WCLK_MUX] =
654 clk[ZX296702_I2S2_WCLK] =
656 clk[ZX296702_I2S2_PCLK] =
659 clk[ZX296702_I2S2_DIV] =
663 if (IS_ERR(clk[i])) {
664 pr_err("zx296702 clk %d: register failed with %ld\n",
665 i, PTR_ERR(clk[i]));
674 CLK_OF_DECLARE(zx296702_lsp0_clk, "zte,zx296702-lsp0crpm-clk",
679 struct clk **clk = lsp1clk;
686 clk[ZX296702_UART0_WCLK_MUX] =
690 * UART does not work after parent clk is disabled/enabled */
691 clk[ZX296702_UART0_WCLK] =
693 clk[ZX296702_UART0_PCLK] =
697 clk[ZX296702_UART1_WCLK_MUX] =
700 clk[ZX296702_UART1_WCLK] =
702 clk[ZX296702_UART1_PCLK] =
706 clk[ZX296702_SDMMC0_WCLK_MUX] =
709 clk[ZX296702_SDMMC0_WCLK_DIV] =
711 clk[ZX296702_SDMMC0_WCLK] =
713 clk[ZX296702_SDMMC0_PCLK] =
716 clk[ZX296702_SPDIF1_WCLK_MUX] =
719 clk[ZX296702_SPDIF1_WCLK] =
721 clk[ZX296702_SPDIF1_PCLK] =
724 clk[ZX296702_SPDIF1_DIV] =
729 if (IS_ERR(clk[i])) {
730 pr_err("zx296702 clk %d: register failed with %ld\n",
731 i, PTR_ERR(clk[i]));
740 CLK_OF_DECLARE(zx296702_lsp1_clk, "zte,zx296702-lsp1crpm-clk",